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Line 1: + + + + + + + + − This page details the packets we will send across our internal Ethernet to define the standards of communication between the digital boards and the controlling PC. Both the FPGA designer and the PC software programmer will need to make reference to this page in order to coordinate their respective designs.+ + + + + + + + + + + + + + + + + + + +
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'''This page deals with material under development. Please be aware that the information here may change as development proceeds.'''
'''This page deals with material under development. Please be aware that the information here may change as development proceeds.'''
This page details the packets we will send across our internal Ethernet to define the standards of communication between the digital boards and the controlling PC. Both the FPGA designer and the PC software programmer will need to make reference to this page in order to coordinate their respective designs.
== Open questions ==
* Will the PC send a layer-2-only packet? Or will the FPGA need to parse out layers 3 and 4?
== Structure of a packet ==
[[Image:Ethernet packet.PNG|thumb|150px|right|A typical Ethernet packet.]]
[[Image:Ethernet packet.PNG|thumb|150px|right|A typical Ethernet packet.]]
To the right is a diagram depicting the structure of an Ethernet packet. On the left side of the diagram is marked the data that will be passed along to the FPGA to be parsed for commands.
'''To be filled in later'''
== Our packets ==
We will use six types of packets in our communications, paired into three "conversations" or "cycles": a reset cycle, a query cycle, a programming cycle. Each packet's data section will begin with a single-byte code to identify the packet type. As a mnemonic, these bytes will use ASCII codes to represent a single-letter shorthand for each packet.
=== The reset cycle ===
The reset cycle is a conversation whose purpose is to reset the digital control board. On each power-on, the various chips on the digital board need to be re-initialized. This includes the Ethernet chip itself, so the reset functionality needs to be built into the FPGA logic by default and needs to execute on start-up with no external stimulus in order to obtain Ethernet control. However it may also be necessary to instigate a reset externally for some reason. This cycle allows the external PC to initiate a reset and will notify the PC when the system is fully initialized.
==== "R" packet: reset ====
This is the packet sent from the PC to the card to initiate a reset process. Two possible reset packet ideas can be considered:
* Full reset: This resets all chips on the board (except for the FPGA; that should reset only during a power-up) together. This will contain no data.
* Selective reset: This will have flags to reset the Ethernet chip, the ADC, the temperature sensor, and the DAC. Combinations of flags allow a selective reset of any combination of the four chips. This will contain four flags which can be packaged into a single byte.
The first data byte will be an ASCII R: 0x52, 0101 0010. For a full-reset-only design, all remaining bytes in the packet will be padding that the FPGA can ignore. For a selective-reset design, the second data byte will contain the four flags, and all bytes after that will be padding.
==== "I" packet: initialization complete ====