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To the right is a diagram depicting the structure of an Ethernet packet. On the left side of the diagram is marked the data that will be passed along to the FPGA to be parsed for commands.
To the right is a diagram depicting the structure of an Ethernet packet. On the left side of the diagram is marked the data that will be passed along to the FPGA to be parsed for commands.
'''To be filled in later'''
'''''To be filled in later'''''
== Our packets ==
== Our packets ==
==== "I" packet: initialization complete ====
==== "I" packet: initialization complete ====
This is the acknowledgment packet sent from the FPGA to the PC to state that the reset cycle has been completed and the digital board is ready to resume regular operations. At this point all settings on the digital board have returned to their defaults (likely to mean all DAC channels set to zero). There is no data associated with this packet, so the only significant byte is the first byte, an ASCII I: 0x49, 0100 1001.
=== The query cycle ===
The query cycle is a conversation regarding the status of the digital board. It polls the sensor devices and reports back their most recent data.
==== "Q" packet: query ====