461
edits
Changes
Jump to navigation
Jump to search
Line 8:
Line 8: +
no edit summary
* What is the clock speed of the FPGA? Timing constraints must be taken into account to link the multiple blocks.
* What is the clock speed of the FPGA? Timing constraints must be taken into account to link the multiple blocks.
* Current designs (11 July, 2007) account for normal activity. Need to design modules/logic for startup and initialization of each component.
* Current designs (11 July, 2007) account for normal activity. Need to design modules/logic for startup and initialization of each component.
* Do the parts work on falling or rising edges of the clock? Most VHDL designs are currently on rising edges, but this can be easily corrected.
== The DAC ==
== The DAC ==