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The control interface to the FPGA core will be:
The control interface to the FPGA core will be:
* ''Clk'': input: Clock line
* ''Clk'': input: Clock line
* ''Rst'': input: Asynchronous, active-low reset line
* ''Go'': input: Pulse to begin transmission
* ''Go'': input: Pulse to begin transmission
* ''Wr'': input: Flag whether or not to write new data to control register
* ''Wr'': input: Flag whether or not to write new data to control register
* ''C(2:0)'': output: Address of data coming from ADC
* ''C(2:0)'': output: Address of data coming from ADC
* ''D(11:0)'': output: Data from ADC
* ''D(11:0)'': output: Data from ADC
* ''Done'': output: Flag to tell core that new data is ready
=== Emulator (A) ===
=== Emulator (A) ===