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[[Image:ISE - RTL.PNG|thumb|left|125px|The Register Transfer Level Schematic.]]
[[Image:ISE - RTL.PNG|thumb|left|125px|The Register Transfer Level Schematic.]]
Once you've synthesized your design, double click on "View RTL Schematic". RTL stands for Register Transfer Level. This gives you what is effectively a block diagram of your circuit, with all the gates and parts in place and wired together. As discussed in previous sections, a thick wire is a bus. By extension, a part drawn with thick lines has bus I/O but performs the same function for all lines of the bus. Inputs are shown on the left as arrows pointing to the right with lines and buses coming off the points of the arrows. Outputs are shown on the right as arrows pointing to the right with lines and buses entering the flat ends of the arrows. Branches of the wires are shown as dots at the intersection points; intersections without dots are separate wires that happen to cross without connecting to each other.
Once you've synthesized your design, double click on "View RTL Schematic". RTL stands for Register Transfer Level. This gives you what is effectively a block diagram of your circuit, with all the gates and parts in place and wired together. As discussed in previous sections, a thick wire is a bus. By extension, a part drawn with thick lines has bus I/O but performs the same function for all lines of the bus. Inputs are shown on the left as arrows pointing to the right with lines and buses coming off the points of the arrows. Outputs are shown on the right as arrows pointing to the right with lines and buses entering the flat ends of the arrows. Branches of the wires are shown as dots at the intersection points; intersections without dots are separate wires that happen to cross without connecting to each other. You can also double click "View Technology Schematic." This is similar to the RTL schematic, however there is no blocking of components together functionally, nor will multiple lines be combined into buses. It can be a rather large, intimidating, and confusing view so it is not often used, as RTL gives the same information in a much more comprehensible fashion.
== Simulation ==
== Simulation ==
Now that you've written your code and seen the RTL schematic (then fixed your code and seen the new RTL schematic and repeated that whole process a few times) it's time to see if it actually works. To do that you need to run a simulation. Unfortunately, it's not that easy; you first need to define a '''test bench waveform''' (.tbw) file.