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<pre>
<pre>
entity component_name is
entity component_name is
Port ( line_in : in STD_LOGIC; -- a single input line
Port ( line_in : in STD_LOGIC; -- a single input line
bus_in1 : in STD_LOGIC_VECTOR (7 downto 2); -- a 6-bit "downto" input bus
bus_in1 : in STD_LOGIC_VECTOR (7 downto 2); -- a 6-bit "downto" input bus
bus_in2 : in STD_LOGIC_VECTOR (0 to 8); -- a 9-bit "to" input bus
bus_in2 : in STD_LOGIC_VECTOR (0 to 8); -- a 9-bit "to" input bus
line_out : out STD_LOGIC; -- a single output line
line_out : out STD_LOGIC; -- a single output line
bus_inout : inout STD_LOGIC_VECTOR (1 to 10); -- a 10-bit bidirectional bus
bus_inout : inout STD_LOGIC_VECTOR (1 to 10) -- a 10-bit bidirectional bus
);
);
end component_name;
end component_name;
</pre>
</pre>
Note that each port in the list is separated by a semicolon, but the last port does not have a semicolon after it. The semicolons in this case are not end-of-line markers, but are list delimiters.