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Note that each port in the list is separated by a semicolon, but the last port does not have a semicolon after it.  The semicolons in this case are not end-of-line markers, but are list delimiters.
 
Note that each port in the list is separated by a semicolon, but the last port does not have a semicolon after it.  The semicolons in this case are not end-of-line markers, but are list delimiters.
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=== Example: coding your black box ===
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The introductory code and port list for the DAC emulator is
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<pre>
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity DAC_emulator is
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    Port ( SCLK     : in STD_LOGIC; -- SCLK
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          invRESET : in STD_LOGIC; -- /RESET
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          invSYNC  : in STD_LOGIC; -- /SYNC
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          D_in     : in STD_LOGIC; -- D_in
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  -- 32 14-bit output channels
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          ch00 : out  STD_LOGIC_VECTOR (13 downto 0);
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          ch01 : out  STD_LOGIC_VECTOR (13 downto 0);
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          ch02 : out  STD_LOGIC_VECTOR (13 downto 0);
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          ch03 : out  STD_LOGIC_VECTOR (13 downto 0);
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          ch04 : out  STD_LOGIC_VECTOR (13 downto 0);
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          ch05 : out  STD_LOGIC_VECTOR (13 downto 0);
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          ch06 : out  STD_LOGIC_VECTOR (13 downto 0);
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          ch07 : out  STD_LOGIC_VECTOR (13 downto 0);
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          ch08 : out  STD_LOGIC_VECTOR (13 downto 0);
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          ch09 : out  STD_LOGIC_VECTOR (13 downto 0);
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          ch10 : out  STD_LOGIC_VECTOR (13 downto 0);
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          ch11 : out  STD_LOGIC_VECTOR (13 downto 0);
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          ch12 : out  STD_LOGIC_VECTOR (13 downto 0);
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          ch13 : out  STD_LOGIC_VECTOR (13 downto 0);
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          ch14 : out  STD_LOGIC_VECTOR (13 downto 0);
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          ch15 : out  STD_LOGIC_VECTOR (13 downto 0);
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          ch16 : out  STD_LOGIC_VECTOR (13 downto 0);
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          ch17 : out  STD_LOGIC_VECTOR (13 downto 0);
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          ch18 : out  STD_LOGIC_VECTOR (13 downto 0);
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          ch19 : out  STD_LOGIC_VECTOR (13 downto 0);
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          ch20 : out  STD_LOGIC_VECTOR (13 downto 0);
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          ch21 : out  STD_LOGIC_VECTOR (13 downto 0);
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          ch22 : out  STD_LOGIC_VECTOR (13 downto 0);
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          ch23 : out  STD_LOGIC_VECTOR (13 downto 0);
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          ch24 : out  STD_LOGIC_VECTOR (13 downto 0);
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          ch25 : out  STD_LOGIC_VECTOR (13 downto 0);
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          ch26 : out  STD_LOGIC_VECTOR (13 downto 0);
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          ch27 : out  STD_LOGIC_VECTOR (13 downto 0);
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          ch28 : out  STD_LOGIC_VECTOR (13 downto 0);
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          ch29 : out  STD_LOGIC_VECTOR (13 downto 0);
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          ch30 : out  STD_LOGIC_VECTOR (13 downto 0);
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          ch31 : out  STD_LOGIC_VECTOR (13 downto 0));
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end DAC_emulator;
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</pre>
     
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