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Line 90: | 
|   |  |   |  | 
|   | Note that each port in the list is separated by a semicolon, but the last port does not have a semicolon after it.  The semicolons in this case are not end-of-line markers, but are list delimiters.  |   | Note that each port in the list is separated by a semicolon, but the last port does not have a semicolon after it.  The semicolons in this case are not end-of-line markers, but are list delimiters.  | 
|   | + |  | 
|   | + | === Example: coding your black box ===  | 
|   | + |  | 
|   | + | The introductory code and port list for the DAC emulator is  | 
|   | + |  | 
|   | + | <pre>  | 
|   | + | library IEEE;  | 
|   | + | use IEEE.STD_LOGIC_1164.ALL;  | 
|   | + | use IEEE.STD_LOGIC_ARITH.ALL;  | 
|   | + | use IEEE.STD_LOGIC_UNSIGNED.ALL;  | 
|   | + |  | 
|   | + | entity DAC_emulator is  | 
|   | + |     Port ( SCLK	    : in STD_LOGIC; -- SCLK  | 
|   | + |            invRESET : in STD_LOGIC; -- /RESET  | 
|   | + |            invSYNC  : in STD_LOGIC; -- /SYNC  | 
|   | + |            D_in	    : in STD_LOGIC; -- D_in  | 
|   | + | 	   -- 32 14-bit output channels  | 
|   | + |            ch00 : out  STD_LOGIC_VECTOR (13 downto 0);  | 
|   | + |            ch01 : out  STD_LOGIC_VECTOR (13 downto 0);  | 
|   | + |            ch02 : out  STD_LOGIC_VECTOR (13 downto 0);  | 
|   | + |            ch03 : out  STD_LOGIC_VECTOR (13 downto 0);  | 
|   | + |            ch04 : out  STD_LOGIC_VECTOR (13 downto 0);  | 
|   | + |            ch05 : out  STD_LOGIC_VECTOR (13 downto 0);  | 
|   | + |            ch06 : out  STD_LOGIC_VECTOR (13 downto 0);  | 
|   | + |            ch07 : out  STD_LOGIC_VECTOR (13 downto 0);  | 
|   | + |            ch08 : out  STD_LOGIC_VECTOR (13 downto 0);  | 
|   | + |            ch09 : out  STD_LOGIC_VECTOR (13 downto 0);  | 
|   | + |            ch10 : out  STD_LOGIC_VECTOR (13 downto 0);  | 
|   | + |            ch11 : out  STD_LOGIC_VECTOR (13 downto 0);  | 
|   | + |            ch12 : out  STD_LOGIC_VECTOR (13 downto 0);  | 
|   | + |            ch13 : out  STD_LOGIC_VECTOR (13 downto 0);  | 
|   | + |            ch14 : out  STD_LOGIC_VECTOR (13 downto 0);  | 
|   | + |            ch15 : out  STD_LOGIC_VECTOR (13 downto 0);  | 
|   | + |            ch16 : out  STD_LOGIC_VECTOR (13 downto 0);  | 
|   | + |            ch17 : out  STD_LOGIC_VECTOR (13 downto 0);  | 
|   | + |            ch18 : out  STD_LOGIC_VECTOR (13 downto 0);  | 
|   | + |            ch19 : out  STD_LOGIC_VECTOR (13 downto 0);  | 
|   | + |            ch20 : out  STD_LOGIC_VECTOR (13 downto 0);  | 
|   | + |            ch21 : out  STD_LOGIC_VECTOR (13 downto 0);  | 
|   | + |            ch22 : out  STD_LOGIC_VECTOR (13 downto 0);  | 
|   | + |            ch23 : out  STD_LOGIC_VECTOR (13 downto 0);  | 
|   | + |            ch24 : out  STD_LOGIC_VECTOR (13 downto 0);  | 
|   | + |            ch25 : out  STD_LOGIC_VECTOR (13 downto 0);  | 
|   | + |            ch26 : out  STD_LOGIC_VECTOR (13 downto 0);  | 
|   | + |            ch27 : out  STD_LOGIC_VECTOR (13 downto 0);  | 
|   | + |            ch28 : out  STD_LOGIC_VECTOR (13 downto 0);  | 
|   | + |            ch29 : out  STD_LOGIC_VECTOR (13 downto 0);  | 
|   | + |            ch30 : out  STD_LOGIC_VECTOR (13 downto 0);  | 
|   | + |            ch31 : out  STD_LOGIC_VECTOR (13 downto 0));  | 
|   | + | end DAC_emulator;  | 
|   | + | </pre>  | 
|   |  |   |  | 
|   |  |   |  |