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*** ''CLK'': clock
*** ''CLK'': clock
*** ''Begin'': active-low input pulse
*** ''Begin'': active-low input pulse
** outputs: 19-cycle pulse
** outputs
*** ''Go'': 19-cycle pulse
* shift register
* shift register
** This is a serial-in, parallel-out, 19-bit shift register. While the enable line is high it clocks in data. The output is nominally partitioned between address and code, but this is implemented not inside the shift register but by routing the output lines appropriately.
** This is a serial-in, parallel-out, 19-bit shift register. While the enable line is high it clocks in data. The output is nominally partitioned between address and code, but this is implemented not inside the shift register but by routing the output lines appropriately.
** inputs: asynchronous, active-low reset; data-in serial line; enable; clock
** inputs
*** ''Reset'': asynchronous, active-low reset
*** ''D_in'': data-in serial line
*** ''En'': enable
*** ''Clk'': clock
** outputs: 5-bit parallel address bus; 14-bit parallel code bus
** outputs: 5-bit parallel address bus; 14-bit parallel code bus
* follow pulse
* follow pulse