Changes

** DB = <math>2^{14}-1</math> (full scale) yields <math>V_{out} = 49.9969*V_{RefIn}</math>.

** DB = <math>2^{14}-1</math> (full scale) yields <math>V_{out} = 49.9969*V_{RefIn}</math>.

The three lines of the interface are ''SYNC'', ''SCLK'', and ''D_in''.  A write to the DAC begins with a falling edge of ''SYNC''.  The next 19 bits (counted off by ''SCLK'') are saved into a shift register  The next transfer begins on another falling edge of ''SYNC'', but transfers do not overlap or interrupt.  A minimum of 200ns is required between exchanges.  '''SCLK''' is ignored except during the 19 shift cycles.  The minimum clock pulse width is 13ns high and 13ns low, yielding a maximum frequency of 77MHz theoretically.  In actual fact the maximum clock frequency is 30MHz and the maximum word frequency is 1.2MHz.  For further details on timing and protocol, see the AD5535 data sheet supplied by Analog Devices, in particular "Timing Characteristics" (p.5) and "Functional Description (p.12).

The three lines of the interface are ''SYNC'', ''SCLK'', and ''D_in''.  A write to the DAC begins with a falling edge of ''SYNC''.  The next 19 bits (counted off by ''SCLK'') are saved into a shift register  The next transfer begins on another falling edge of ''SYNC'', but transfers do not overlap or interrupt.  A minimum of 200ns is required between exchanges.  ''SCLK'' is ignored except during the 19 shift cycles.  The minimum clock pulse width is 13ns high and 13ns low, yielding a maximum frequency of 77MHz theoretically.  In actual fact the maximum clock frequency is 30MHz and the maximum word frequency is 1.2MHz.  For further details on timing and protocol, see the AD5535 data sheet supplied by Analog Devices, in particular "Timing Characteristics" (p.5) and "Functional Description (p.12).

=== Emulator ===

=== Emulator ===

* 19-cycle hold

* 19-cycle hold

** This block takes the single input pulse (one clock cycle wide) and generates a 19-cycle-wide pulse to tell the shift register how long to read in new data.  It ignores any additional pulses while the 19-cycle pulse is running.  It also enforces a gap of one cycle between serial words.

** This block takes the single input pulse (one clock cycle wide) and generates a 19-cycle-wide pulse to tell the shift register how long to read in new data.  It ignores any additional pulses while the 19-cycle pulse is running.  It also enforces a gap of one cycle between serial words.

** inputs: asynchronous, active-low reset; clock; active-low input pulse

** inputs

*** ''Reset'': asynchronous, active-low reset

*** ''CLK'': clock

*** ''Begin'': active-low input pulse

** outputs: 19-cycle pulse

** outputs: 19-cycle pulse

* shift register

* shift register