SiPM digital control board netlist
Overview
This page contains a listing of the pins of all major ICs that will be used in the SiPM digital control board, sorted by what they will be connected to. This list is mostly complete, but will be expanded and corrected as the project progresses.
To see connections in reference to available power supply voltages, see SiPM digital control board power supplies.
Legend
The following table describes the ICs as they are referenced on this page. Clicking a component name will bring you to the component's datasheet.
IC Name | Description |
AD7928 | 8 channel analog-to-digital converter |
AD5535 | 32 channel digital-to-analog converter |
AD7314 | 10-bit temperature sensor |
CP2201 | Ethernet controller |
XCF01S | Xilinx Platform Flash EEPROM, Model XCF01S |
XC3S50A | Xilinx Spartan-3A field programmable gate array (FPGA) |
FPGA Connections
This section defines some pins that must be on the FPGA, and what they must connect to. Many of these connections may also be found in the IC netlist.
User I/O pins
For these I/O pins, "Pin Name" defines the name of the pins as they will be used for our project, not the actual pin name in the FPGA schematic. The physical FPGA pins used for each of these connections will be determined later to optimize the circuitry around the FPGA.
Pin Name | Description | Connect To |
CLK_OUT | 5MHz clock output subdivded from main 20MHz clock | AD7314 pin 3, AD7928 pin 1, AD5535 pin P9 |
ETH_INT | Ethernet interrupt request pin | CP2201 pin 25 |
ETH_CS | Ethernet chip select | CP2201 pin 24 |
ETH_RD | Ethernet read strobe | CP2201 pin 22 |
ETH_WR | Ethernet write strobe | CP2201 pin 23 |
ETH_AD0 | Ethernet address/data bus | CP2201 pin 11 |
ETH_AD1 | Ethernet address/data bus | CP2201 pin 12 |
ETH_AD2 | Ethernet address/data bus | CP2201 pin 13 |
ETH_AD3 | Ethernet address/data bus | CP2201 pin 14 |
ETH_AD4 | Ethernet address/data bus | CP2201 pin 15 |
ETH_AD5 | Ethernet address/data bus | CP2201 pin 16 |
ETH_AD6 | Ethernet address/data bus | CP2201 pin 17 |
ETH_AD7 | Ethernet address/data bus | CP2201 pin 18 |
ETH_ALE | Ethernet ALE strobe | CP2201 pin 21 |
TEMP_CE | Temperature sensor enable | AD7314 pin 2 |
TEMP_IN | Input from temperature sensor | AD7314 pin 5 |
DAC_OUT | Serial output to DAC | AD5535 pin P8 |
ADC_OUT | Serial output to ADC | AD7928 pin 2 |
ADC_IN | Serial input from ADC | AD7928 pin 18 |
ADC_CS | Chip select for ADC | AD7928 pin 3 |
ID0 | Board identifier bit 0 | Backplane |
ID1 | Board identifier bit 1 | Backplane |
ID2 | Board identifier bit 2 | Backplane |
ID3 | Board identifier bit 3 | Backplane |
ID4 | Board identifier bit 4 | Backplane |
ID5 | Board identifier bit 5 | Backplane |
ID6 | Board identifier bit 6 - not used - tied to ground | Backplane |
ID7 | Board identifier bit 7 - not used - tied to ground | Backplane |
Configuration Pins
These pins are used for the programming of the FPGA. Many of these pins revert to user I/O pins after programming is complete.
We will be using the master serial (Platform Flash) programming mode (see FPGA programming modes). Configuration pins not used in this mode are omitted from the table below. The connections that are in the table are also visually described on page 16 of the XCF01S data sheet.
Pin Name | Description | During Programming Connect To |
After Programming Connect To |
Notes |
M0 | Mode select pin for configuration | Ground | User I/O | Should be <0:0:0> during configuration to indicate master serial mode |
M1 | Mode select pin for configuration | Ground | User I/O | |
M2 | Mode select pin for configuration | Ground | User I/O | |
DONE | Programming complete pin | XCF01S CE, pin 10 | XCF01S CE, pin 10 | Goes high when programming is complete |
PROG_B | Initiates programming process | XCF01S CF, pin 7 | XCF01S CF, pin 7 | Low causes master reset of FPGA High initiates programming after reset Should be high for normal operation |
CCLK | Clock for programming | XCF01S CLK, pin 3 | User I/O | If M[2:0] define a master mode, CCLK is internally generated If M[2:0] define a slave mode, CCLK is a clock input |
INIT_B | Programming status indicator | XCF01S OE/RESET, pin 8 | User I/O, or high or low | Before programming, low indicates internal memory is being cleared During programming, low indicates CRC error After programming, should be driven high or low if not used for user I/O |
PUDC_B | User I/O pull-up control | ??? | User I/O | Set low during programming to enable pull-ups on all user I/O pins after configuration |
DIN | Serial data input | XCF01S D0, pin 1 | User I/O | Serial data input from XCF01S |
DOUT | Serial data output | No connection | User I/O | Used to daisy chain to next FPGA, if this were a multi-FPGA design We are using only one FPGA per PCB, so this is not used |
IC netlist
This table lists the pins on the four main ICs and shows what they should be connected to. For the FPGA pin connections, see the next section.
IC | Pin # | Pin Name | Connect To | Notes |
AD5535 | N3 | CATHODE | AD7928 Vin6 and resistor to ground | Cathode of internal diode for temperature monitoring |
AD5535 | N4 | ANODE | +3.3V rail | Anode of internal diode for temperature monitoring |
AD7314 | 3 | SCLK | Clock, 5 MHz, FPGA CLK_OUT | Clock input for serial data output control |
AD7928 | 1 | SCLK | Clock, 5 MHz, FPGA CLK_OUT | Used for reading data and conversion |
AD5535 | P9 | SCLK | Clock, 5 MHz, FPGA CLK_OUT | |
CP2201 | 27 | XTAL2 | Clock, 20MHz Crystal, Excitation Driver Input | |
CP2201 | 28 | XTAL1 | Clock, 20MHz Crystal, Output | |
CP2201 | 25 | INT | FPGA | Interrupt service request |
CP2201 | 24 | CS | FPGA | Chip select |
CP2201 | 22 | RD | FPGA | Read strobe |
CP2201 | 23 | WR | FPGA | Write strobe |
CP2201 | 11 | AD0 | FPGA | Address/data bit |
CP2201 | 12 | AD1 | FPGA | Address/data bit |
CP2201 | 13 | AD2 | FPGA | Address/data bit |
CP2201 | 14 | AD3 | FPGA | Address/data bit |
CP2201 | 15 | AD4 | FPGA | Address/data bit |
CP2201 | 16 | AD5 | FPGA | Address/data bit |
CP2201 | 17 | AD6 | FPGA | Address/data bit |
CP2201 | 18 | AD7 | FPGA | Address/data bit |
CP2201 | 21 | ALE | FPGA | ALE Strobe |
AD7314 | 2 | CS (CE) | FPGA | Chip select |
AD7314 | 5 | SDO | FPGA | Serial data output |
AD7314 | 6 | SDI | Ground | Serial data in - will not be used |
AD5535 | P8 | DIN | FPGA | Serial data input, must be valid at falling edge of SCLK |
AD7928 | 2 | DIN | FPGA | Data in |
AD7928 | 3 | CS | FPGA | Chip select |
AD7928 | 18 | DOUT | FPGA | Serial data out - see spec sheet for details |
AD7314 | 7 | ID | FPGA? | Identifies chip in SPI bus system |
AD5535 | P10 | SYNC | FPGA? | Frame synchronization signal. Data transferred when low |
CP2201 | 2 | AGND | Ground | |
CP2201 | 9 | DGND1 | Ground | |
CP2201 | 20 | DGND2 | Ground | |
CP2201 | 26 | MOTEN | Ground | Ground indicates Intel bus format |
AD7314 | 4 | GND | Ground | |
AD5535 | H4 | AGND | Ground | |
AD5535 | H5 | AGND | Ground | |
AD5535 | H6 | AGND | Ground | |
AD5535 | H7 | AGND | Ground | |
AD5535 | H8 | AGND | Ground | |
AD5535 | H9 | AGND | Ground | |
AD5535 | H10 | AGND | Ground | |
AD5535 | H11 | AGND | Ground | |
AD5535 | J3 | AGND | Ground | |
AD5535 | J4 | AGND | Ground | |
AD5535 | J5 | AGND | Ground | |
AD5535 | J6 | AGND | Ground | |
AD5535 | J7 | AGND | Ground | |
AD5535 | J8 | AGND | Ground | |
AD5535 | J9 | AGND | Ground | |
AD5535 | J10 | AGND | Ground | |
AD5535 | J11 | AGND | Ground | |
AD5535 | J12 | AGND | Ground | |
AD5535 | K3 | AGND | Ground | |
AD5535 | K4 | AGND | Ground | |
AD5535 | K5 | AGND | Ground | |
AD5535 | K6 | AGND | Ground | |
AD5535 | K7 | AGND | Ground | |
AD5535 | K8 | AGND | Ground | |
AD5535 | K9 | AGND | Ground | |
AD5535 | K10 | AGND | Ground | |
AD5535 | K11 | AGND | Ground | |
AD5535 | K12 | AGND | Ground | |
AD5535 | K13 | AGND | Ground | |
AD5535 | K14 | AGND | Ground | |
AD5535 | L3 | AGND | Ground | |
AD5535 | L4 | AGND | Ground | |
AD5535 | L5 | AGND | Ground | |
AD5535 | L6 | AGND | Ground | |
AD5535 | L7 | AGND | Ground | |
AD5535 | L8 | AGND | Ground | |
AD5535 | L9 | AGND | Ground | |
AD5535 | L10 | AGND | Ground | |
AD5535 | L11 | AGND | Ground | |
AD5535 | L12 | AGND | Ground | |
AD5535 | L13 | AGND | Ground | |
AD5535 | L14 | DAC_GND | Ground | |
AD5535 | M1 | AGND | Ground | |
AD5535 | M2 | AGND | Ground | |
AD5535 | M3 | AGND | Ground | |
AD5535 | M4 | AGND | Ground | |
AD5535 | M5 | AGND | Ground | |
AD5535 | M6 | AGND | Ground | |
AD5535 | M7 | AGND | Ground | |
AD5535 | M8 | AGND | Ground | |
AD5535 | M9 | AGND | Ground | |
AD5535 | M10 | AGND | Ground | |
AD5535 | M11 | AGND | Ground | |
AD5535 | M12 | AGND | Ground | |
AD5535 | N1 | PGND | Ground | Output amplifier ground reference |
AD5535 | N2 | PGND | Ground | |
AD5535 | N5 | AGND | Ground | |
AD5535 | N6 | AGND | Ground | |
AD5535 | N7 | AGND | Ground | |
AD5535 | N8 | AGND | Ground | |
AD5535 | N9 | AGND | Ground | |
AD5535 | N10 | AGND | Ground | |
AD5535 | N11 | AGND | Ground | |
AD5535 | N12 | AGND | Ground | |
AD5535 | N13 | AGND | Ground | |
AD5535 | N14 | AGND | Ground | |
AD5535 | P3 | DAC_GND | Ground | |
AD5535 | P6 | DGND | Ground | |
AD5535 | P11 | AGND | Ground | |
AD5535 | P12 | AGND | Ground | |
AD5535 | P13 | AGND | Ground | |
AD7928 | 4 | AGND | Ground | |
AD7928 | 8 | AGND | Ground | |
AD7928 | 17 | AGND | Ground | |
AD7928 | 20 | AGND | Ground | |
CP2201 | 10 | RST | High/low switch | Resets controller when low for 15us |
AD5535 | P4 | RESET | High/low switch | Resets controller when low |
AD5535 | P7 | TEST | High/low switch | Should be LOW when not testing |
AD7314 | 1 | NC | No connection | |
AD5535 | A1 | NC | No connection | |
AD5535 | A14 | NC | No connection | |
AD5535 | P1 | NC | No connection | |
AD5535 | P14 | NC | No connection | |
AD7928 | 19 | VDRIVE | Power supply, 3.3V | Sets voltage at which DOUT operates |
AD5535 | P2 | REF_IN | Power supply, 1 to 4V | Programs full scale output from 50-200V |
AD7928 | 7 | REF_IN | Power supply, 2.5V | Must be accurate to +/-1% |
AD7314 | 8 | VDD | Power Supply, 2.65 to 5.5V | |
AD5535 | P5 | DVCC | Power supply, 2.7 to 5.25V | Digital supply pin |
AD7928 | 5 | AVDD | Power supply, 2.7 to 5.25V | Should be 4.75 to 5.25V for 0 to 2xREF_IN range |
AD7928 | 6 | AVDD | Power supply, 2.7 to 5.25V | Should be 4.75 to 5.25V for 0 to 2xREF_IN range |
CP2201 | 3 | AV+ | Power Supply, 3.1 to 3.6V | |
CP2201 | 8 | VDD1 | Power Supply, 3.1 to 3.6V | |
CP2201 | 19 | VDD2 | Power Supply, 3.1 to 3.6V | |
AD5535 | K1 | V+ | Power supply, 4.75 to 5.25V | Amplifier supply pin |
AD5535 | K2 | V+ | Power supply, 4.75 to 5.25V | Amplifier supply pin |
AD5535 | M13 | AVCC | Power supply, 4.75 to 5.25V | Analog supply pin |
AD5535 | M14 | AVCC | Power supply, 4.75 to 5.25V | Analog supply pin |
AD5535 | L1 | V- | Power supply, -4.75 to -5.25V | Amplifier supply pin |
AD5535 | L2 | V- | Power supply, -4.75 to -5.25V | Amplifier supply pin |
AD5535 | H1 | VFF | Power supply, high voltage | Range can be REF_INx50 + anywhere from 10 to 225V |
CP2201 | 4 | RX- | RJ-45 Connector, Negative Receive Wire | |
CP2201 | 7 | TX- | RJ-45 Connector, Negative Transmit Wire | |
CP2201 | 5 | RX+ | RJ-45 Connector, Positive Receive Wire | |
CP2201 | 6 | TX+ | RJ-45 Connector, Positive Transmit Wire | |
AD5535 | A2 | Vout1 | SiPM Bias Voltage Input | |
AD5535 | A4 | Vout7 | SiPM Bias Voltage Input | |
AD5535 | A6 | Vout11 | SiPM Bias Voltage Input | |
AD5535 | A8 | Vout18 | SiPM Bias Voltage Input | |
AD5535 | A10 | Vout20 | SiPM Bias Voltage Input | |
AD5535 | A12 | Vout25 | SiPM Bias Voltage Input | |
AD5535 | B1 | Vout0 | SiPM Bias Voltage Input | |
AD5535 | B3 | Vout4 | SiPM Bias Voltage Input | |
AD5535 | B5 | Vout9 | SiPM Bias Voltage Input | |
AD5535 | B7 | Vout13 | SiPM Bias Voltage Input | |
AD5535 | B9 | Vout17 | SiPM Bias Voltage Input | |
AD5535 | B11 | Vout21 | SiPM Bias Voltage Input | |
AD5535 | B13 | Vout26 | SiPM Bias Voltage Input | |
AD5535 | C2 | Vout3 | SiPM Bias Voltage Input | |
AD5535 | C12 | Vout22 | SiPM Bias Voltage Input | |
AD5535 | C14 | Vout29 | SiPM Bias Voltage Input | |
AD5535 | D1 | Vout2 | SiPM Bias Voltage Input | |
AD5535 | D13 | Vout23 | SiPM Bias Voltage Input | |
AD5535 | E2 | Vout5 | SiPM Bias Voltage Input | |
AD5535 | E4 | Vout8 | SiPM Bias Voltage Input | |
AD5535 | E6 | Vout12 | SiPM Bias Voltage Input | |
AD5535 | E8 | Vout15 | SiPM Bias Voltage Input | |
AD5535 | E10 | Vout19 | SiPM Bias Voltage Input | |
AD5535 | E12 | Vout24 | SiPM Bias Voltage Input | |
AD5535 | E14 | Vout31 | SiPM Bias Voltage Input | |
AD5535 | F3 | Vout6 | SiPM Bias Voltage Input | |
AD5535 | F5 | Vout10 | SiPM Bias Voltage Input | |
AD5535 | F7 | Vout14 | SiPM Bias Voltage Input | |
AD5535 | F9 | Vout18 | SiPM Bias Voltage Input | |
AD5535 | F13 | Vout30 | SiPM Bias Voltage Input | |
AD5535 | G14 | Vout28 | SiPM Bias Voltage Input | |
AD5535 | H13 | Vout27 | SiPM Bias Voltage Input | |
AD7928 | 16 | Vin0 | +1.2V rail | See SiPM digital control board power supplies |
AD7928 | 15 | Vin1 | +2.5V rail | |
AD7928 | 14 | Vin2 | +3.3V rail | |
AD7928 | 13 | Vin3 | +5V rail | |
AD7928 | 12 | Vin4 | -5V rail | |
AD7928 | 11 | Vin5 | Cathode of AD5535 temperature diode | |
AD7928 | 10 | Vin6 | ??? | Should be used for any other voltage that must be monitored |
AD7928 | 9 | Vin7 | ??? | Should be used for any other voltage that must be monitored |
CP2201 | 1 | LA | Backplane to external LED (outside of the tagger) | LED will be connected outside of the tagger to keep the chamber as dark as possible |