Changes

* The term '''signal''' is sometimes used to generically refer to a line, pin, or bus.  Later you will see that the ''proper'' use of the term signal is to discuss an internal line or bus.  However, as pins are connected to internal lines and buses, sometimes sloppy terminology extends "signal" to include pins.

* The term '''signal''' is sometimes used to generically refer to a line, pin, or bus.  Later you will see that the ''proper'' use of the term signal is to discuss an internal line or bus.  However, as pins are connected to internal lines and buses, sometimes sloppy terminology extends "signal" to include pins.

* Signals come in '''active-high''' and '''active-low''' varieties.  Active-high means that a logical 1 is "on" and a logical 0 is "off".  It is also known as "positive logic".  Active-low is the exact opposite; logical 0 is "on" and logical 1 is "off", and it is alternately known as "negative logic".

* Signals come in '''active-high''' and '''active-low''' varieties.  Active-high means that a logical 1 is "on" and a logical 0 is "off".  It is also known as "positive logic".  Active-low is the exact opposite; logical 0 is "on" and logical 1 is "off", and it is alternately known as "negative logic".

* Some signals serve double-duty.  As active-high logic they perform one operation, but as active-low logic they perform another operation.  This links these operations as complimentary pairs.  For example a shift register may shift its output or it may load a new value.  If it's not shifting then it's loading.  So the name would be something like "Shift/Load" to signify that shifting is active-high and loading is active-low.  Carrying over this notation, any signal that is written "/Name" is an active-low signal.  This notation is not always used, but it is quite common and I shall attempt to maintain this practice throughout the tutorial.  When writing on paper, an active-low signal is frequently denoted by an overbar instead of a leading slash.  Unless otherwise specified, a signal that is not marked as active-low is assumed to be active-high by default.  Some designs assume active-low as the default, but that will either be marked or implied by context (i.e. all active-high lines marked as such).

* Some signals serve double-duty.  As active-high logic they perform one operation, but as active-low logic they perform another operation.  This links these operations as complimentary pairs.  For example a shift register may shift its output or it may load a new value.  If it's not shifting then it's loading.  So the name would be something like "Shift/Load" to signify that shifting is active-high and loading is active-low.  Carrying over this notation, any signal that is written "/Name" is an active-low signal.  This notation is not always used, but it is quite common and I shall attempt to maintain this practice throughout the tutorial.  When writing on paper, an active-low signal is frequently denoted by an overbar instead of a leading slash.  Unless otherwise specified, a signal that is not marked as active-low is assumed to be active-high by default.  Some designs assume active-low as the default, but that will either be marked or implied by context (e.g. all active-high lines marked as such).

* A '''pin''' is an input, output, or inout.  A '''line''' is a single pin or a single bit of data flowing along a wire.  A '''bus''' is properly a multidrop line, but through common usage (due to the way circuits are commonly designed), in digital logic at this level the term has come to mean multiple lines bound together into a bundle.  On a diagram, a bus appears as a thick line with a slash through it.  Near the slash will be a number denoting how many lines are bundled into that bus.

* A '''pin''' is an input, output, or inout.  A '''line''' is a single pin or a single bit of data flowing along a wire.  A '''bus''' is properly a multidrop line, but through common usage (due to the way circuits are commonly designed), in digital logic at this level the term has come to mean multiple lines bound together into a bundle.  On a diagram, a bus appears as a thick line with a slash through it.  Near the slash will be a number denoting how many lines are bundled into that bus.

== Example: the block box ==

== Example: the block box ==

For the DAC emulator, the inputs are clearly defined for us.  The AD5535 data sheet discusses the [[Programming_the_FPGA#Interface_.28D.29|serial interface protocol]] in detail.  We need four input lines:

For the DAC emulator, the inputs are clearly defined for us.  The AD5535 data sheet discusses the [[Programming_the_DAC#Interface|serial interface protocol]] in detail.  We need four input lines:

* ''/Reset'': an asynchronous, active-low reset line

* ''/Reset'': an asynchronous, active-low reset line

* ''D_in'': serial data line

* ''D_in'': serial data line

== The block diagram ==

== The block diagram ==

Having defined your block box, you need to fill in your black box.  But before doing that, we need to note the different between two types of logic:

Having defined your block box, you need to fill in your black box.  But before doing that, we need to note the difference between two types of logic:

* ''Combinational logic'' merely recombines lines into new lines.  For example, signal Q may be the logical AND of signals A, B, and C.  There is no reference to a clock in combinational logic.

* ''Combinational logic'' merely recombines lines into new lines.  For example, signal Q may be the logical AND of signals A, B, and C.  There is no reference to a clock in combinational logic.

* ''Sequential logic'' is any logic that makes use of a clock for latches, flip-flops, registers, or other devices.  Sequential logic changes only when the clock changes.  Often circuits are wired so that all sequential logic changes together, either on a ''falling edge'' of a clock or a ''rising edge'' of a clock.  Advanced designs can change some components on a rising edge and other components on a falling edge, but this is significantly more difficult due to the tighter timing restrictions imposed.

* ''Sequential logic'' is any logic that makes use of a clock for latches, flip-flops, registers, or other devices.  Sequential logic changes only when the clock changes.  Often circuits are wired so that all sequential logic changes together, either on a ''falling edge'' of a clock or a ''rising edge'' of a clock.  Advanced designs can change some components on a rising edge and other components on a falling edge, but this is significantly more difficult due to the tighter timing restrictions imposed.

[[Image:DAC_Emulator_Block.JPG|thumb|Functional block diagram of the DAC emulator.]]

[[Image:DAC_Emulator_Block.JPG|thumb|Functional block diagram of the DAC emulator.]]

The block diagram is shown to the right, and each block is described on the [[Programming_the_FPGA#Emulator_.28D.29|FPGA programming page]].  Note that the repeated blocks (the 32 terminal registers) are not all drawn.  Two or three are generally sufficient to illustrate connections (for example, does a line feed all 32, or are there 32 separate lines?).  Ellipses are perfectly acceptable.

The block diagram is shown to the right, and each block is described on the [[Programming_the_DAC#Emulator|FPGA programming page]].  Note that the repeated blocks (the 32 terminal registers) are not all drawn.  Two or three are generally sufficient to illustrate connections (for example, does a line feed all 32, or are there 32 separate lines?).  Ellipses are perfectly acceptable.