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− | The modules involved in communication with the Ethernet Controller chip (EC) serve as the core of the FPGA. The different tasks that need to be performed by these modules include | + | The modules involved in communication with the Ethernet Controller chip (EC) serve as the core of the FPGA. The tasks that need to be performed by these modules include |
| * executing the complex board reset and address lookup sequence | | * executing the complex board reset and address lookup sequence |
| * polling for new packets and switching execution accordingly | | * polling for new packets and switching execution accordingly |
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| ! State !! Module Name !! Description !! Succeeding State | | ! State !! Module Name !! Description !! Succeeding State |
| |- | | |- |
− | | align="center" | 000 || [[FPGA_Reset|Reset]]_hard || align="left" |Coordinates the reset and start-up of the EC. || 101 | + | | align="center" | 000 || [[FPGA_Reset|Reset]]_hard || align="left" |Coordinates the reset and start-up of the EC. || 100 |
| |- | | |- |
− | | align="center" | 001 || [[FPGA_Reset|Reset]]_soft || align="left" | Extends the reset to the PC-requested chips and records PC's MAC for later communication. || 101 | + | | align="center" | 001 || [[FPGA_Reset|Reset]]_soft || align="left" | Extends the reset to the PC-requested chips and records PC's MAC for later communication. || 100 |
| |- | | |- |
| | align="center" | 010 || [[FPGA_Idler|Idler]] || align="left" | This is the active module during the FPGA's default idle state. It awaits the "Receive FIFO buffer not empty" interrupt and passes control to the Reader || 011 | | | align="center" | 010 || [[FPGA_Idler|Idler]] || align="left" | This is the active module during the FPGA's default idle state. It awaits the "Receive FIFO buffer not empty" interrupt and passes control to the Reader || 011 |
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| |- | | |- |
| |} | | |} |
− |
| |
| | | |
| === State interconnect === | | === State interconnect === |
| | | |
| As described above, these states form the outline of the functional block diagram. This implementation calls for a central ''state register''. Each block reads the state value in the register and enables itself upon seeing its own value. After completion of its function, a block will write a new value to the state register to enable the next block. With several modules writing to the register, usual precautions must be taken to avoid more than one drivers forcing a line simultaneously. All modules must be designed to go to high impedance on their output lines when they are not active. | | As described above, these states form the outline of the functional block diagram. This implementation calls for a central ''state register''. Each block reads the state value in the register and enables itself upon seeing its own value. After completion of its function, a block will write a new value to the state register to enable the next block. With several modules writing to the register, usual precautions must be taken to avoid more than one drivers forcing a line simultaneously. All modules must be designed to go to high impedance on their output lines when they are not active. |
| + | |
| + | |
| + | == Miscellaneous non-state-based components == |
| + | |
| + | Please refer to the individual design detail pages for: |
| + | * [[FPGA_Registers|Registers]] |
| + | * [[FPGA_Reusables|Miscellaneous Reusable Components]] |
| + | |
| | | |
| == Interface == | | == Interface == |
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| | | |
| This communication standard calls for a bridge module that communicates with the EC upon request from other modules. A "[[FPGA_Transceiver|Transceiver]]" was designed for this purpose. It abstracts the communication with the EC as well as the clock frequency difference. This module in fact subdivides the main 20 MHz; clock to generate the "slow" 5 MHz clock for the rest of the FPGA. Please refer to the [[FPGA_Transceiver|detailed page]] on the Transceiver for more information. | | This communication standard calls for a bridge module that communicates with the EC upon request from other modules. A "[[FPGA_Transceiver|Transceiver]]" was designed for this purpose. It abstracts the communication with the EC as well as the clock frequency difference. This module in fact subdivides the main 20 MHz; clock to generate the "slow" 5 MHz clock for the rest of the FPGA. Please refer to the [[FPGA_Transceiver|detailed page]] on the Transceiver for more information. |
| + | |
| | | |
| == Combined control flow == | | == Combined control flow == |
| | | |
− | [[Image:DigBoardScheme.png|center]] | + | [[Image:OperationCourse.png|frame|Operation course between the digital board and the controller PC]] |
| | | |
| + | Conceptually, the operation course must proceed as outlined in the adjacent figure. The main concern in the tagger control is maintaining a map between board/channel addresses and actual energy bins. For this purpose, the diagrammed two-stage reset plan was devised in the course of which the FPGA learns the PC's MAC address and the PC builds a MAC-Location lookup table. (The "Location" is an 8-byte slot identifier which allows the PC to pinpoint the SiPM channel group.) |
| | | |
− | == Miscellaneous non-state-based components ==
| + | The internal FPGA operation course that supports this scheme (and the general control board functionality requirements) is outlined below. |
− | | |
− | Please refer to the individual design detail pages for:
| |
− | * [[FPGA_Registers|Registers]]
| |
− | * [[FPGA_Reusables|Miscellaneous Reusable Components]]
| |
| | | |
| + | [[Image:DigBoardScheme.png|center]] |
| | | |
| | | |
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| | | |
| * Non-state Modules | | * Non-state Modules |
− | ** [[FPGA_Transceiver]] | + | ** [[FPGA_Transceiver|Transceiver]] |
− | ** [[FPGA_Registers]] | + | ** [[FPGA_Interrupt_Catcher|Interrupt Catcher]] |
| + | ** [[FPGA_Registers|Registers]] |
| | | |
| * [[Ethernet_packets|Ethernet Packet formatting]] | | * [[Ethernet_packets|Ethernet Packet formatting]] |