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Programming the Ethernet controller (view source)
Revision as of 03:20, 29 October 2009
, 03:20, 29 October 2009→State-Module organization
! State !! Module Name !! Description !! Succeeding State
! State !! Module Name !! Description !! Succeeding State
|-
|-
| align="center" | 000 || [[FPGA_Reset|Reset]]_hard || align="left" |Coordinates the reset and start-up of the EC. || 101
| align="center" | 000 || [[FPGA_Reset|Reset]]_hard || align="left" |Coordinates the reset and start-up of the EC. || 100
|-
|-
| align="center" | 001 || [[FPGA_Reset|Reset]]_soft || align="left" | Extends the reset to the PC-requested chips and records PC's MAC for later communication. || 101
| align="center" | 001 || [[FPGA_Reset|Reset]]_soft || align="left" | Extends the reset to the PC-requested chips and records PC's MAC for later communication. || 101
|-
|-
|}
|}
=== State interconnect ===
=== State interconnect ===