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Programming the Ethernet controller (view source)
Revision as of 22:24, 5 June 2008
, 22:24, 5 June 2008→Combined control flow
== Combined control flow ==
== Combined control flow ==
[[Image:OperationCourse.png|thumb|340px|Operation course between the digital board and the controller PC]]
Conceptually, the operation course must proceed as outlined in the adjacent figure. The main concern in the tagger control is maintaining a map between board/channel addresses and actual energy bins. For this purpose, the diagrammed two-stage reset plan was devised in the course of which the FPGA learns the PC's MAC address and the PC builds a MAC-Location lookup table. (The "Location" is an 8-byte slot identifier which allows the PC to pinpoint the SiPM channel group.)
The internal FPGA operation course that supports this scheme (and the general control board functionality requirements) is outlined below.
[[Image:DigBoardScheme.png|center]]
[[Image:DigBoardScheme.png|center]]
== Miscellaneous non-state-based components ==
== Miscellaneous non-state-based components ==