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* <s>''A_out'': 8-bit bus for address of last read/write</s>
 
* <s>''A_out'': 8-bit bus for address of last read/write</s>
 
* ''D_out'': 8-bit bus for data of last read; internal systems should ignore for a write
 
* ''D_out'': 8-bit bus for data of last read; internal systems should ignore for a write
 +
* ''CLK'' : 5MHz clock for all internals subdivided from the master 20MHz clock.
    
outputs to CP2200/1
 
outputs to CP2200/1
1,004

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