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Programming the Ethernet controller (view source)
Revision as of 17:15, 19 December 2007
, 17:15, 19 December 2007→Registers
outputs
outputs
* ''Q'': three-bit data-out bus
* ''Q'': three-bit data-out bus
=== Packet Type Register ===
An 8-bit register to store the 2nd byte of an accepted packet.
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
* ''En'': write enable
* ''D'': 8-bit data-in bus
outputs
* ''Q'': 8-bit data-out bus
outputs
outputs
* ''Q'': 16-bit data-out bus (data pre-padded with 2 zeros to facilitate packaging into 2-byte words)
* ''Q'': 16-bit data-out bus (data pre-padded with 2 zeros to facilitate packaging into 2-byte words)
== Reusable Components ==
== Reusable Components ==