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Line 142: Line 142:  
|3
 
|3
 
|SCLK
 
|SCLK
|FPGA CLK_OUT
+
|Clock, 5 MHz, FPGA CLK_OUT
 
|5MHz Clock input for serial data output control
 
|5MHz Clock input for serial data output control
 
|----
 
|----
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