Changes

It essential to avoid clipping the signal at designed gain levels and to be able to utilize the full range (2 V) of the ADC. Appropriate DC level were set to avoid saturation any transistor collectors. This turns out a bit involved, since the collector-base voltage (plus the canonical saturation margin of 100 mV) gap necessary is more than the maximum desired signal of 2 V due to attenuation along the amplifier chain. Changing DC levels changes biasing of transistor bases, changing the quiescent current and therefore the attenuation. Additionally the power budget significantly restricts the DC levels of the circuit.  

It essential to avoid clipping the signal at designed gain levels and to be able to utilize the full range (2 V) of the ADC. Appropriate DC level were set to avoid saturation any transistor collectors. This turns out a bit involved, since the collector-base voltage (plus the canonical saturation margin of 100 mV) gap necessary is more than the maximum desired signal of 2 V due to attenuation along the amplifier chain. Changing DC levels changes biasing of transistor bases, changing the quiescent current and therefore the attenuation. Additionally the power budget significantly restricts the DC levels of the circuit.  

In the current stage of the design, full 2V range has not been achieved. Both single channel and summing outputs ago up to about 1.5 V.  

In the current stage of the design, full 2V range has not been achieved. Both single channel and summing outputs go up to about 1.5 V.

 

==== The Gain Switch ====

==== The Gain Switch ====