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== Incorrect footprint for the Ethernet Jack used ==
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== Ethernet jack pinout mismatch  ==
 
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[please fill in the part information]
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The wrong Ethernet jack was attached to the PCB, leading to a pinout mismatch. The part ordered was the Pulse J001'''1'''D21. The correct part is J001'''2'''D21. The correct part was ordered and soldered onto the prototype boards, but this change must be made in the Altium parts list.
    
= Suggested/Preferred Changes =
 
= Suggested/Preferred Changes =
    
* <code>R12</code>, the pull-up resistor for the reset pins (header 2) is unnecessary, as the FPGA pin can be programmed to pull up.
 
* <code>R12</code>, the pull-up resistor for the reset pins (header 2) is unnecessary, as the FPGA pin can be programmed to pull up.
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