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Digital control board debugging notes (view source)
Revision as of 16:10, 22 June 2009
, 16:10, 22 June 2009no edit summary
This page contains a list of all currently known problems with the digital control board.
== No Power on +1.2V Power Island ==
=== Description ===
The +1.2V island was found to be at 0.0V rather than +1.2V.
=== Cause ===
The +5V input (pin 2) on the +1.2V voltage regulator, VR3 (Analog Devices ADP1715), was not connected.
=== Solution ===
A dab of solder was used to short pins 1 and 2 on VR3. Pin 1 is an active high chip enable pin, which is permanently tied to +5V.
=== Other Details and Current Status ===
This problem was due to an unconnected pin in the original schematics. The schematics have '''not yet been updated''' to reflect the solution.
* June 22, 2009: One board has been modified to correct this problem.
== SPI Bus Miswired ==
=== Description ===
The SPI bus to the temperature sensor and the ADC is not wired correctly.
=== Cause ===
FPGA pin 5 (labelled SPI) is connected to DIN on the ADC, and DOUT of the temperature sensor. FPGA pin 96 (labelled AD7928/DOUT) is connected to DOUT on the ADC. SPI designates that all slave device DOUT traces be connected together. Chip select and HiZ logic are used to prevent devices from fighting over the signal line.
=== Solution ===
DOUT on the temperature sensor should be connected to DOUT on the ADC and pin 96 on the FPGA. This can be accomplished by cutting the existing DOUT trace near the temperature sensor and soldering a wire to DOUT on the ADC. DIN on the ADC can then be connected with a wire to pin 5 on the FPGA, or if possible, simply left connected using the original trace. In this configuration, pin 5 on the FPGA will become the SPI MOSI (master out, slave in) line, and pin 96 on the FPGA will become the SPI MISO (master in, slave out) line. DIN on the temperature sensor is left tied to ground, since it is not needed.
=== Other Details and Current Status ===
This problem was due to errors int he original schematics. The schematics have '''not yet been updated''' to reflect the solution.
* June 22, 2009: This modification has not yet been implemented.
== No Power on +1.2V Power Island ==
=== Description ===
The +1.2V island was found to be at 0.0V rather than +1.2V.
=== Cause ===
The +5V input (pin 2) on the +1.2V voltage regulator, VR3 (Analog Devices ADP1715), was not connected.
=== Solution ===
A dab of solder was used to short pins 1 and 2 on VR3. Pin 1 is an active high chip enable pin, which is permanently tied to +5V.
=== Other Details and Current Status ===
This problem was due to an unconnected pin in the original schematics. The schematics have '''not yet been updated''' to reflect the solution.
* June 22, 2009: One board has been modified to correct this problem.
== SPI Bus Miswired ==
=== Description ===
The SPI bus to the temperature sensor and the ADC is not wired correctly.
=== Cause ===
FPGA pin 5 (labelled SPI) is connected to DIN on the ADC, and DOUT of the temperature sensor. FPGA pin 96 (labelled AD7928/DOUT) is connected to DOUT on the ADC. SPI designates that all slave device DOUT traces be connected together. Chip select and HiZ logic are used to prevent devices from fighting over the signal line.
=== Solution ===
DOUT on the temperature sensor should be connected to DOUT on the ADC and pin 96 on the FPGA. This can be accomplished by cutting the existing DOUT trace near the temperature sensor and soldering a wire to DOUT on the ADC. DIN on the ADC can then be connected with a wire to pin 5 on the FPGA, or if possible, simply left connected using the original trace. In this configuration, pin 5 on the FPGA will become the SPI MOSI (master out, slave in) line, and pin 96 on the FPGA will become the SPI MISO (master in, slave out) line. DIN on the temperature sensor is left tied to ground, since it is not needed.
=== Other Details and Current Status ===
This problem was due to errors int he original schematics. The schematics have '''not yet been updated''' to reflect the solution.
* June 22, 2009: This modification has not yet been implemented.