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Digital control board documentation (view source)
Revision as of 20:42, 16 June 2009
, 20:42, 16 June 2009→Pinout Table
===Pinout Table===
===Pinout Table===
Note that the header is positioned on the board rotated 180 degrees from the position in which it is shown in the Xilinx documentation. Care must be taken when connecting the flying leads to ensure they are connected to the right pins. Improper wiring will certainly cause undesired operation, and may cause damage as well. Damage is most likely to occur if one of the flying leads is connected to an odd numbered pin, since it will short to the PCB's ground plane. '''Note from the pinout table below that no flying lead connections should ever be made to the odd numbered pins on the JTAG header.'''
Note that the header is positioned on the board rotated 180 degrees from the position in which it is shown in the Xilinx documentation. Care must be taken when connecting the flying leads to ensure they are connected to the right pins. Improper wiring will certainly cause undesired operation, and may cause damage as well. Damage is most likely to occur if one of the flying leads is improperly connected to an odd numbered pin, since it will short to the PCB's ground plane.
{| cellpadding=3 border=1 |
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Pin #'''
| '''Net Name'''
| '''Net Name'''
| '''Flying Lead'''
| '''Description'''
| '''Description'''
|-
|-
| 1, 3, 5, 7, 9, 11, 13 (odd pins)
| 1, 3, 5, 7, 9, 11, 13 (odd pins)
| DGND
| DGND
| Ground pins for signal integrity<br>'''Never connect a flying lead to these pins'''<br>Doing so will short to ground and may cause permanent damage if the Platform USB II cable does not have protection against this.
| Black (connect to any odd numbered pin)
| Ground pins for signal integrity<br>'''Never connect a flying lead other than the black lead to an odd numbered pin'''<br>Doing so will short to ground and may cause permanent damage if the Platform USB II cable does not have protection against this.
|-
|-
| 2
| 2
| +3.3V
| +3.3V
| <span style="color: red">Red/VREF</span>
| Power source for all JTAG logic
| Power source for all JTAG logic
|-
|-
| 4
| 4
| FPGA/TMS
| FPGA/TMS
| <span style="color: green">Green/TMS</span>
| JTAG TMS - connects to EEPROM and FPGA
| JTAG TMS - connects to EEPROM and FPGA
|-
|-
| 6
| 6
| FPGA/TCK
| FPGA/TCK
| <span style="color: yellow">Yellow/TCK</span>
| JTAG TCK - connects to EEPROM and FPGA
| JTAG TCK - connects to EEPROM and FPGA
|-
|-
| 8
| 8
| FPGA/TDO
| FPGA/TDO
| <span style="color: purple">Purple/TDO</span>
| JTAG boundary scan chain endpoint
| JTAG boundary scan chain endpoint
|-
|-
| 10
| 10
| EEPROM/TDI
| EEPROM/TDI
| White/TDI
| JTAG boundary scan chain start point
| JTAG boundary scan chain start point
|-
|-
| 12
| 12
| No connection
| No connection
|
| Pin is floating
| Pin is floating
|-
|-
| 14
| 14
| No connection
| No connection
|
| Pin is floating
| Pin is floating
|}
|}
''The gray HALT flying lead is not connected.''
===JTAG Overview===
===JTAG Overview===