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| + | |
| + | == Ethernet Controller == |
| + | The board uses a Silicon Laboratories CP2201, 28-pin, ethernet controller. The CP2201 is located just above the FPGA, and is labelled U2. |
| + | |
| + | === Power Details === |
| + | The CP2201 uses only +3.3V, which is supplied by the +3.3V power plane and regulated by VR1. Appropriate decoupling capacitors can be found near the CP2201. |
| + | |
| + | === Ethernet Jack === |
| + | To the right of the CP2201 is a Pulse J0011D21NL ethernet jack, labelled J1. This jack has a built-in 1:1 inductive coupling. For best results, connect this jack to a nearby ethernet switch. The jack may also be connected directly to a computer using a crossover cable. Though auto-crossover is not supported by the CP2201, if the computer's NIC supports it, a crossover cable is not necessary to connect directly to a computer. |
| + | |
| + | === Crystal Oscillator === |
| + | The CP2201 is responsible for driving the 20MHz crystal oscillator. This oscillator clocks both the CP2201 and the FPGA. The crystal oscillator can be found above the right corner of the FPGA. It can be identified by its four surface mount pads and roughly .3" length. It is labelled Y1, though this label is not visible after the oscillator is soldered on. The CP2201 uses an inverting driver to excite the crystal. The output of hte crystal is then sent to the CP2201 and the FPGA. |
| + | |
| + | === Bus Format and Multiplexing === |
| + | The 28-pin CP2201 used on the board only supports multiplexed operation. This means that both address and data information is passed over the same set of 8 traces. Hence, these traces are referred to as the address/data (AD) bus. A separate address line enable (ALE) trace prevents collisions from occuring on these traces. The communication protocol used is the Intel format. See the CP2201's datasheet for more information about this. |
| + | |
| + | === Pinout Table === |