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→Ports
[[FPGA_Registers#MAC_Register|MAC Address Register]] Control Lines
[[FPGA_Registers#MAC_Address_Registers|MAC Address Register]] Control Lines
* ''MACregs_En'': [out] register enable (write) signal
* ''MACregs_En'': [out] register enable (write) signal
* ''MACregs_A'': [out] byte address (4-bit)
* ''MACregs_A'': [out] byte address (4-bit)
* ''dbShort'': [in] debug signal to bypass EC reset waiting periods
* ''dbShort'': [in] debug signal to bypass EC reset waiting periods
== Programming Details of Rest_soft ==
== Programming Details of Rest_soft ==