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SiPM Amplifier Optimization (view source)
Revision as of 05:33, 5 February 2009
, 05:33, 5 February 2009no edit summary
The low impedance input stage was retained from the earlier design and applied the the summing circuit, since it pools currents from the individual amplifiers. In Photonique's design, the input signal sees the transistor base, base-biasing resistor, and a feedback resistor in parallel. The new input stages take the signal on the emitter (base held at a set DC value), in which case the signal sees the emitter resistor and the impedance looking into the emitter in parallel with each other. The latter dominates with an effective resistance of order 25 Ω. The input stages are biased with generous amount of current to keep this value low.
The low impedance input stage was retained from the earlier design and applied the the summing circuit, since it pools currents from the individual amplifiers. In Photonique's design, the input signal sees the transistor base, base-biasing resistor, and a feedback resistor in parallel. The new input stages take the signal on the emitter (base held at a set DC value), in which case the signal sees the emitter resistor and the impedance looking into the emitter in parallel with each other. The latter dominates with an effective resistance of order 25 Ω. The input stages are biased with generous amount of current to keep this value low.
==== <math>\beta</math>-dependence and Voltage Buffering ====
==== <math>\beta</math>-dependence and Voltage Buffering ====
[[Image:AmpVis_v6_DC.png|frame|center|DC characteristics of the amplifier. Units of V, mA, and Ω are implied unless corrected by different prefix.]]
[[Image:AmpVis_v6_DC.png|frame|center|DC characteristics of the amplifier. Units of V, mA, and Ω are implied unless corrected by different prefix.]]
==== Dynamic Range ====
It essential to avoid clipping the signal at designed gain levels and to be able to utilize the full range (2 V) of the ADC. Appropriate DC level were set to avoid saturation any transistor collectors. This turns out a bit involved, since the collector-base voltage (plus the canonical saturation margin of 100 mV) gap necessary is more than the maximum desired signal of 2 V due to attenuation along the amplifier chain. Changing DC levels changes biasing of transistor bases, changing the quiescent current and therefore the attenuation. Additionally the power budget significantly restricts the DC levels of the circuit.
In the current stage of the design, full 2V range has not been achieved. Both single channel and summing outputs ago up to about 1.5 V.
==== The Gain Switch ====
==== The Gain Switch ====
A MOSFET switch the effective collector resistor in the first stage of the summing circuit between about 3 kΩ due to R<sub>e</sub> alone and the parallel path of 165 Ω. NXP's BF1108R has been selected for prototyping. Its typical <math>V_{GS}</math> for current pinch-off is -3 V (max: -4 V). Putting its source on the supply rail and switching the gate between 5 V (on) and 0 V (off). A bypass capacitor (not shown in diagram) near the gate lead is important to prevent spurious switching.
A MOSFET switch the effective collector resistor in the first stage of the summing circuit between about 3 kΩ due to R<sub>e</sub> alone and the parallel path of 165 Ω. NXP's BF1108R has been selected for prototyping. Its typical <math>V_{GS}</math> for current pinch-off is -3 V (max: -4 V). Putting its source on the supply rail and switching the gate between 5 V (on) and 0 V (off). A bypass capacitor (not shown in diagram) near the gate lead is important to prevent spurious switching.