Changes

To keep single channel and summing circuit readout independent of each other, a separate driver for the summing circuit was added. The first stage of the amplifier contains a switchable collector resistance which, the ratio of which with the effective resistance of the driver sets the additional gain sought at this stage. The additional inversion (to a positive-going signal) must be countered with another inverter, followed by the voltage buffer similar to that at the end of the single channel amplifier circuit.

To keep single channel and summing circuit readout independent of each other, a separate driver for the summing circuit was added. The first stage of the amplifier contains a switchable collector resistance which, the ratio of which with the effective resistance of the driver sets the additional gain sought at this stage. The additional inversion (to a positive-going signal) must be countered with another inverter, followed by the voltage buffer similar to that at the end of the single channel amplifier circuit.

Signal buffering turns out to be tricky in this project. The requirement of negative output pulse polarity set by the ADC mandates a PNP transistor for the final stages of both amplifier and summing segments. However, the &beta; characteristics of the only acceptable fast PNP found on the market (BFT92W) are even worse than those in its NPN counterpart. The typical value of <math>h_{FE}</math> is 50 with a minimum value of 20, compared to BFR92P from Infineon, which sports values from 70 to near 100. The effective load of the terminators of about <math>\beta 50~\Omega</math> remains comparable to the source impedance of the circuit. In other words, the source impedance cannot be considered negligible compared to the load, creating an effective voltage divider whose ration depends on beta! Since the output from the summing circuit suffers from about twice as much variation due to &beta; because of all the preceding stages, a stiffer buffer became essential on this end. The emitter-follower driver was doubled, effectively multiply the &beta;'s of the two transistors. The resulting two diode drops, too low to avoid significant saturation on collectors of earlier stages, are countered with a DC level shift with AC coupling from preceding circuit elements.

Signal buffering turns out to be tricky in this project. The requirement of negative output pulse polarity set by the ADC mandates a PNP transistor for the final stages of both amplifier and summing segments. However, the &beta; characteristics of the only acceptable fast PNP found on the market (BFT92W) are even worse than those in its NPN counterpart. The typical value of <math>h_{FE}</math> is 50 with a minimum value of 20, compared to BFR92P from Infineon, which sports values from 70 to near 100. The effective load of the terminators of about &beta;50&nbsp;&Omega remains comparable to the source impedance of the circuit. In other words, the source impedance cannot be considered negligible compared to the load, creating an effective voltage divider whose ration depends on beta! Since the output from the summing circuit suffers from about twice as much variation due to &beta; because of all the preceding stages, a stiffer buffer became essential on this end. The emitter-follower driver was doubled, effectively multiply the &beta;'s of the two transistors. The resulting two diode drops, too low to avoid significant saturation on collectors of earlier stages, are countered with a DC level shift with AC coupling from preceding circuit elements.

[[Image:AmpVis_v6_DC.png|DC characteristics of the amplifier. Units of V, mA, and &Omega; are implied unless corrected by different prefix.]]

[[Image:AmpVis_v6_DC.png|DC characteristics of the amplifier. Units of V, mA, and &Omega; are implied unless corrected by different prefix.]]