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Line 227: − − Since some of the configuration pins are used for user I/O after programming, a set of logic gates might be necessary to ensure the XCF01S remains disabled following programming. By simply ORing or NORing appropriate signals with the DONE signal, integrity of user I/O signals and signals to the XCF01S can be ensured.
SiPM digital control board netlist (view source)
Revision as of 15:47, 26 June 2008
, 15:47, 26 June 2008→Configuration Pins: removed EEPROM isolating logic information
|[http://www.xilinx.com/products/silicon_solutions/proms/pfp/spartan.htm Xilinx Platform Flash EEPROM], Model XCF01S
|[http://www.xilinx.com/products/silicon_solutions/proms/pfp/spartan.htm Xilinx Platform Flash EEPROM], Model XCF01S
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|[http://www.xilinx.com/support/documentation/data_sheets/ds529.pdf FPGA]
|[http://www.xilinx.com/support/documentation/data_sheets/ds529.pdf XC3S50A]
|Xilinx Spartan-3A field programmable gate array
|Xilinx Spartan-3A field programmable gate array (FPGA)
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|}
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== IC netlist ==
== IC netlist ==