Changes

The Xilinx XCF01S EEPROM is responsible for configuring the FPGA when the system is turned on or reset. We selected the XCF01S because it is recommended by Xilinx as the best solution for programming the Spartan-3A FPGA used on the control board. The XCF01S is ideal because it has sufficient memory to hold the entire FPGA program, and also minimizes the number of FPGA-to-EEPROM leads necessary for programming the FPGA. For more information on the mode of programming the FPGA, see [[FPGA programming modes]].

The Xilinx XCF01S EEPROM is responsible for configuring the FPGA when the system is turned on or reset. We selected the XCF01S because it is recommended by Xilinx as the best solution for programming the Spartan-3A FPGA used on the control board. The XCF01S is ideal because it has sufficient memory to hold the entire FPGA program, and also minimizes the number of FPGA-to-EEPROM leads necessary for programming the FPGA. For more information on the mode of programming the FPGA, see [[FPGA programming modes]].

TODO: Insert information about logic levels.

Both the EEPROM and the FPGA are designed to tolerate +3.3V CMOS logic levels, keeping the configuration logic at the same voltages as the other logic on the board.

=== Post-Configuration EEPROM Isolating Logic ===

=== Post-Configuration EEPROM Isolating Logic ===

It may be necessary to introduce OR gates and NOR gates (with the FPGA's DONE pin) to keep EEPROM pins at the necessary logic values after programming is complete, if the configuration pins on the FPGA will be reused as user I/O pins following configuration. Research must be done into whether this logic is necessary. The specifications sheet for the XCF01S says that when CE is held high, the D0 pin goes into a high impedance state. What is not clear is if changing logic values on the others pins will have an adverse effect when CE is high.

Originally it was though that it may be necessary to introduce OR gates and NOR gates (with the FPGA's DONE pin) to keep EEPROM pins at the necessary logic values after programming is complete, if the configuration pins on the FPGA were to be reused as user I/O pins following configuration. However, the specifications sheet for the XCF01S says that when CE is held high, the D0 pin goes into a high impedance state. We believe this is sufficient to prevent unwanted EEPROM I/O operations due to changing logic levels on its pins following configuration, meaning post-configuration EEPROM isolating logic is not necessary. In addition, due to the large number of available I/O pins on the FPGA, there are sufficient dedicated I/O pins available so that these shared pins do not need to be reused in our design.

=== FPGA/EEPROM Pull-up Resistors ===

=== FPGA/EEPROM Pull-up Resistors ===

As shown in the [[:Image:SiPM FPGA and EEPROM Connections.gif |connection diagram]], 4.7kΩ pull-up resistors are necessary to pull up the DONE, INIT_B and PROG_B pins to VCCO.

Despite being shown in the [[:Image:SiPM FPGA and EEPROM Connections.gif |connection diagram]], 4.7kΩ pull-up resistors are not necessary to pull up the DONE, INIT_B and PROG_B pins to VCCO, since we will be enabling internal pull-ups using the PUDC_B pin.

== CP2201 Ethernet Supporting Components ==

== CP2201 Ethernet Supporting Components ==

=== LED-less RJ-45 Jack ===

=== LED-less RJ-45 Jack ===

Since we want to keep the enclosure as dark as possible, we must use an Ethernet jack with no built-in activity/link LED. There are many suitable jacks available. Most likely, we will want a shielded jack such as the Stewart Connector Systems SS-6488S-A-NF ([http://search.digikey.com/scripts/DkSearch/dksus.dll?pname?site=us;lang=en;name=380-1024-ND Digi-Key Part #380-1024-ND]). However, there are many other LED-less jacks available that may also be suitable. For a listing of other LED-less jacks, look at the [http://digi-key.dirxion.com/Main.asp?from=emailafriend&pagenav=&bookid=2&pageindex=306 Digi-Key Interactive Catalog].

Since we want to keep the enclosure as dark as possible, we must use an Ethernet jack with no built-in activity/link LED. There are many suitable jacks available. The jack we have selected to use on the board is the Pulse Engineering J0012D21.