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SiPM digital control board supporting components (view source)
Revision as of 15:10, 25 June 2008
, 15:10, 25 June 2008→FPGA Supporting Components: more FPGA supporting components
[[Image:SiPM FPGA and EEPROM Connections.gif|thumb|Connection diagram for XCF01S and Spartan-3A FPGA taken from<br>[http://www.xilinx.com/support/documentation/data_sheets/ds123.pdf XCF01S specifications sheet].]]
[[Image:SiPM FPGA and EEPROM Connections.gif|thumb|Connection diagram for XCF01S and Spartan-3A FPGA taken from<br>[http://www.xilinx.com/support/documentation/data_sheets/ds123.pdf XCF01S specifications sheet].]]
The Xilinx XCF01S EEPROM is responsible for configuring the FPGA when the system is turned on or reset. We selected the XCF01S because it is recommended by Xilinx as the best solution for programming the Spartan-3A FPGA used on the control board. The XCF01S is ideal because it has sufficient memory to hold the entire FPGA program, and also minimizes the number of FPGA-to-EEPROM leads necessary for programming the FPGA.
The Xilinx XCF01S EEPROM is responsible for configuring the FPGA when the system is turned on or reset. We selected the XCF01S because it is recommended by Xilinx as the best solution for programming the Spartan-3A FPGA used on the control board. The XCF01S is ideal because it has sufficient memory to hold the entire FPGA program, and also minimizes the number of FPGA-to-EEPROM leads necessary for programming the FPGA. For more information on the mode of programming the FPGA, see [[FPGA programming modes]].
TODO: Insert information about logic levels.
TODO: Insert information about logic levels.
=== Post-Configuration EEPROM Isolating Logic ===
It may be necessary to introduce OR gates and NOR gates (with the FPGA's DONE pin) to keep EEPROM pins at the necessary logic values after programming is complete, if the configuration pins on the FPGA will be reused as user I/O pins following configuration. Research must be done into whether this logic is necessary. The specifications sheet for the XCF01S says that when CE is held high, the D0 pin goes into a high impedance state. What is not clear is if changing logic values on the others pins will have an adverse effect when CE is high.
=== FPGA/EEPROM Pull-up Resistors ===
As shown in the [[:Image:SiPM FPGA and EEPROM Connections.gif |connection diagram]], 4.7kΩ pull-up resistors are necessary to pull up the DONE, INIT_B and PROG_B pins to VCCO.