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SiPM digital control board netlist (view source)
Revision as of 20:16, 24 June 2008
, 20:16, 24 June 2008→Configuration Pins: added description of possible logic necessary between FPGA and EEPROM
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+Since some of the configuration pins are used for user I/O after programming, a set of logic gates might be necessary to ensure the XCF01S remains disabled following programming. By simply ORing or NORing appropriate signals with the DONE signal, integrity of user I/O signals and signals to the XCF01S can be ensured.
== IC netlist ==
== IC netlist ==