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Line 227: − |---- − |VS0 − |Variant select pin for SPI mode programming − |Not used − |User I/O − | rowspan=3 | Not used, since we are not using SPI mode programming − |---- − |VS1 − |Variant select pin for SPI mode programming − |Not used − |User I/O − |---- − |VS2 − |Variant select pin for SPI mode programming − |Not used − |User I/O − |---- − |MOSI − |Serial data output to SPI EEPROM − |Not used − |User I/O − |Used for EEPROM read commands in only SPI mode programming<br>Not used in our configuration − |---- − |CSO_B − |Chip select output for SPI − |Not used − |User I/O − |Used for SPI mode only
SiPM digital control board netlist (view source)
Revision as of 19:49, 24 June 2008
, 19:49, 24 June 2008→Configuration Pins: removed references to configuration pins for other programming modes
These pins are used for the programming of the FPGA. Many of these pins revert to user I/O pins after programming is complete.
These pins are used for the programming of the FPGA. Many of these pins revert to user I/O pins after programming is complete.
We will be using the master serial (Platform Flash) programming mode (see [[FPGA programming modes]]). Configuration pins not used in this mode are omitted from the table below.
{| cellspacing=3 border=1 |
{| cellspacing=3 border=1 |
|'''Pin Name'''
|'''Pin Name'''
|User I/O
|User I/O
|Used to daisy chain to next FPGA, if this were a multi-FPGA design<br>We are using only one FPGA per PCB, so this is not used
|Used to daisy chain to next FPGA, if this were a multi-FPGA design<br>We are using only one FPGA per PCB, so this is not used
|----
|----
|}
|}