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→Master serial (platform flash) mode: added brief overview of interface with platform flash chips
For information about the other pins used in the programming process, see [[SiPM digital control board netlist]].
For information about the other pins used in the programming process, see [[SiPM digital control board netlist]].
=== Master serial (platform flash) mode ===
=== Master serial (Platform Flash) mode ===
Operating in master serial mode, the FPGA generates its own clock signal during the programming process. This clock signal is output through the FPGA's CCLK pin (see [[SiPM digital control board netlist#Configuration pins | FPGA Configuration Pins]]). When used with a compatible [http://www.xilinx.com/products/silicon_solutions/proms/pfp/spartan.htm Xilinx EEPROM], the FPGA can read data from the EEPROM by driving the EEPROM's CE and OE pins high, and waiting for CF to rise. New data is available on the D0 pin a short while after each rising clock edge.