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=== State Register ===
=== State Register ===
A three-bit register to store the current state.
A three-bit register to store the current state.
inputs
inputs
* ''Clk'': clock
* ''Clk'': clock
=== MAC Address Registers ===
=== MAC Address Registers ===
A set of eight 12-bit registers to store the most recent ADC data. Also includes a demultiplexer to select which register to write to. In practice there is a 16-bit-wide bus on output: the 12-bit data is pre-padded with zeros for the convenience of other modules.
A set of 12 8-bit registers to store the board's and PC's MAC addresses (in that order). Note that all bits of the register are set high upon reset as a simple way to ensure that packets sent to the PC before its address has been learned will be interpreted as a broadcast packet.
inputs
inputs
=== DAC Registers ===
=== DAC Registers ===
A set of 32 14-bit registers to store the most recent DAC data. Also includes a demultiplexer to select which register to write to. In practice there is a 16-bit-wide bus on output: the 14-bit data is pre-padded with zeros for the convenience of other modules.
A set of 32 14-bit registers to store the most recent DAC data. Also includes a demultiplexer to select which register to write to. In practice there is a 16-bit-wide bus on output: the 14-bit data is pre-padded with zeros for the convenience of other modules.
inputs
inputs
* ''Clk'': clock
* ''Clk'': clock