Changes

The '''SiPM digital control board''' is the communication block for controlling the SiPMs.  It provides the interface through which an external system can control or monitor the SiPMs.

The '''SiPM digital control board''' is the communication block for controlling the SiPMs.  It provides the interface through which an external system can control or monitor the SiPMs. Additionally, it serves as an outlet of amplified SiPM signals.

One of the remaining questions about the design of this board is the number of SiPMs channels.  For more detail, see [[SiPM_digital_control_board#The_DAC|the section on the DAC]].

 

Design of the control board is an ongoing project, so more questions may be added later.

* Size of the FPGA in terms of logic gates and I/O pins.  For more detail, see [[SiPM_digital_control_board#The_FPGA|the section on the FPGA]].

* Number of SiPMs per digital control card.  For more detail, see [[SiPM_digital_control_board#The_DAC|the section on the DAC]].

== Responsibilities of the control board ==

== Responsibilities of the control board ==

The data sheet, user guide, configuration guide, and other documentation regarding the FPGA can be downloaded from the [http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=Publications/FPGA+Device+Families/Spartan-3A Xilinx website].

The data sheet, user guide, configuration guide, and other documentation regarding the FPGA can be downloaded from the [http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=Publications/FPGA+Device+Families/Spartan-3A Xilinx website].

Much of the FPGA programming is concerned with the complex operations of the Ethernet controller chip [[#The Ethernet controller|CP2200/1 discussed below]]. This core interacts with the DAC and SPI (bus for ADC and Temperature sensor) controller modules when access to these chips is required.

Much of the FPGA programming is concerned with the complex operations of the Ethernet controller chip [[#The Ethernet controller|CP2200/1 discussed below]]. This core interacts with the DAC and SPI (bus for ADC and Temperature sensor) controller modules when access to these chips is required. Please see the relevant pages from the following list.

* [[Programming the DAC]]

* [[Programming the Ethernet controller (core of FPGA design)]]

* [[Programming the SPI]]

** [[Reset and Initialization]] - discussion of reset/initialization needs of our chips.

* [[Programming the Ethernet controller]]

* [[Programming the DAC controller]]

* [[Reset and Initialization]]

* [[Programming the SPI controller]]

=== The Ethernet controller ===

=== The Ethernet controller ===

After researching a variety of communication buses, including USB, I²C, FireWire, and various others, it was decided that the best choice would be Ethernet.  Ethernet is based on a multi-layer protocol, with each higher layer adding more advanced capabilities.  Only layers one and two are necessary for our purposes, being a local network not connected to a true internet.  We have selected the Silicon Laboratories CP2200/1 Ethernet controller.  The CP2200 and CP2201 are the same chip with the differences lying (primarily) in packaging and I/O pin count.  Likely the CP2201 (the smaller chip) will prove sufficient, however as of June 2007 that decision has not been finalized. The CP2200/1 supplies layers one and two automatically and can interface with the FPGA through a parallel bus described by the CP2200/1 data sheet.

After researching a variety of communication buses, including USB, I²C, FireWire, and various others, it was decided that the best choice would be Ethernet.  Ethernet is based on a multi-layer protocol, with each higher layer adding more advanced capabilities.  Only layers one and two are necessary for our purposes, being a local network not connected to a true internet.  We have selected the Silicon Laboratories CP2200/1 Ethernet controller.  The two variants of the chip differ (primarily) in packaging and I/O pin count: the CP2201 requires a ''Multiplexed'' Intel Bus interface, saving many pins. The FPGA has been designed around this chip.

The data sheet and other information regarding the Ethernet controller can be downloaded from the [http://www.silabs.com/tgwWebApp/public/web_content/products/Microcontrollers/Interface/en/CP220x.htm Silicon Laboratories website].

The data sheet and other information regarding the Ethernet controller can be downloaded from the [http://www.silabs.com/tgwWebApp/public/web_content/products/Microcontrollers/Interface/en/CP220x.htm Silicon Laboratories website].

[[Image:SPI-like bus.JPG|thumb|SPI-like bus topology]]

[[Image:SPI-like bus.JPG|thumb|SPI-like bus topology]]

In order to monitor the voltage levels of the power lines, an ADC is to be included in the design.  The Analog Devices' AD7928 is an eight-channel ADC.  Based on the selection of components there are six necessary power lines and two necessary grounds, so the AD7928 is capable of monitoring the entire system if need be.  It uses a serial protocol that is compatible with the SPI bus to communicate with the FPGA.

In order to monitor the voltage levels of the power lines and possibly some DAC channels, an ADC is to be included in the design.  The Analog Devices' AD7928 is an eight-channel ADC.  Based on the selection of components there are six necessary power lines and two necessary grounds, so the AD7928 is capable of monitoring the entire system if need be.  It uses a serial protocol that is compatible with the SPI bus to communicate with the FPGA.

The data sheet and other information regarding the ADC can be downloaded from the [http://www.analog.com/en/prod/0%2C2877%2CAD7928%2C00.html Analog Devices website].

The data sheet and other information regarding the ADC can be downloaded from the [http://www.analog.com/en/prod/0%2C2877%2CAD7928%2C00.html Analog Devices website].