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inputs
inputs
* ''Clk'': clock
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
* ''Rst'': asynchronous, reset to zero the register (puts system into reset state)
* ''En'': write enable
* ''En'': write enable
* ''D'': three-bit data-in bus
* ''D'': three-bit data-in bus
=== Packet Type Register ===
=== Packet Type Register ===
An 8-bit register to store the 2nd byte of an accepted packet.
An 8-bit register to store the 2nd byte of an accepted packet.
inputs
* ''Clk'': clock
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
* ''Rst'': asynchronous reset to zero the register
* ''En'': write enable
* ''En'': write enable
* ''D'': 8-bit data-in bus
* ''D'': 8-bit data-in bus
inputs
inputs
* ''Clk'': clock
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
* ''Rst'': asynchronous reset to zero the register
* ''En'': write enable
* ''En'': write enable
* ''D'': 10-bit data-in bus
* ''D'': 10-bit data-in bus
inputs
inputs
* ''Clk'': clock
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
* ''Rst'': asynchronous reset to zero the register
* ''En'': write enable
* ''En'': write enable
* ''A'': 3-bit address
* ''A'': 3-bit address
=== DAC Registers ===
=== DAC Registers ===
A set of 32/24/16 16-bit registers to store the most recent DAC data. Also includes a demultiplexer to select which register to write to.
A set of 32 16-bit registers to store the most recent DAC data. Also includes a demultiplexer to select which register to write to.
inputs
inputs
* ''Clk'': clock
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
* ''Rst'': asynchronous reset to zero the register
* ''En'': write enable
* ''En'': write enable
* ''A'': 5/5/4-bit address (currently set at 5-bit)
* ''A'': 5-bit address
* ''D'': 14-bit data-in bus
* ''D'': 14-bit data-in bus
outputs
outputs
* ''Q'': 16-bit data-out bus (data pre-padded with 2 zeros to facilitate packaging into 2-byte words)
* ''Q'': 16-bit data-out bus (data pre-padded with 2 zeros to facilitate packaging into 2-byte words)