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Line 1: − == (100) Query Sensor Chips ==+ − + + + + − This block will have at least two functional blocks: one to poll the temperature sensor and one to poll the ADC. Its job is to update all status values from the status chips in preparation for transmission. Additionally, it converts all values to 16-bit two's-complement before storing locally. Once all status values have been updated it transitions to state 101.+ − Currently we assume that data values will be stored in the FPGA. If data values will be stored on CP2200/1 Flash memory or other storage device, the interfaces and blocks will have to be adjusted appropriately.+ + − inputs − * ''Clk'': clock − * ''/Rst'': asynchronous, active-low reset − * ''State'': 3-bit state value − internal signals+ − + − + + + − blocks+ − * '''ADC Poll'''+ − ** Updates values stored in the FPGA from the ADC. Obtains data from ADC, converts to 16-bit two's-complement, and stores.+ − ** inputs+ − *** ''Clk'': clock+ − *** ''/Rst'': asynchronous, active-low reset+ − *** ''Go'': go pulse to begin+ − ** outputs+ − *** - All ADC control lines -+ − *** ''A_Done'': goes high when reset/initialization process is complete, falls on ''Go'' pulse+ − *** ''En'': enable line for writing to the internal registers+ − *** ''Sel'': 3-bit select bus to specify which ADC channel data is available+ − *** ''Data'': 16-bit data bus to carry data to FPGA internal registers+ − * '''Temp Poll'''+ − ** Updates value stored in the FPGA from the temperature sensor. Obtains data from temperature sensor, converts to 16-bit two's-complement, and stores.+ − ** inputs+ − *** ''Clk'': clock+ − *** ''/Rst'': asynchronous, active-low reset+ − *** ''Go'': go pulse to begin+ − ** outputs − *** - All temperature sensor control lines - − *** ''En'': enable line for writing to the internal register − *** ''Data'': 16-bit data bus to carry data to FPGA internal registers − * '''Coordinator''' − ** Coordinates the completion of each polling cycle and notifies other blocks that the polling process is complete. − ** inputs − *** ''Clk'': clock − *** ''/Rst'': asynchronous, active-low reset − *** ''A_Done'': high when ADC is done polling − ** outputs − *** ''Done'': when ''A_Done'' goes high, ''Done'' pulses for one cycle; connects to state register as an enable − **: Note that the temperature sensor does not signal completion. That is because the temperature sensor need only update one value, while the ADC must update eight values. Thus it is known ahead of time that the temperature sensor will already be done by the time the ADC is done. − *** ''New_St'': new state to be written to the state register; goes to 101 while ''Done'' is high
no edit summary
:''See also [[Programming_the_Ethernet_controller|Programming the Ethernet Controller]]'' for a survey of modules and a general discussion of FPGA design approach.''
:''See also [[Programming_the_Ethernet_controller|Programming the Ethernet Controller]]'' for a survey of modules and a general discussion of FPGA design approach.''
= (100) Query Sensor Chips =
The Querier performs a poll of the sensor chips: Temperature Sensor and the 8-channel ADC. The returned values from these combined nine polls are stored in the [[FPGA_Registers#Temperature Register|Temperature and ADC registers]].
The Querier performs a poll of the sensor chips: Temperature Sensor and the 8-channel ADC. The returned values from these combined nine polls are stored in the [[FPGA_Registers#Temperature Register|Temperature and ADC registers]]. The Querier always passes control to the Transmitter in order to relay an S (status) packet to the PC with the polled values.
Minor error-handling is built into this module. When the 3-bit ADC address returned from the [[Programming_the_SPI|SPI module]] after a query does not match the requested channel a 0xFFF value is written for that voltage value.
== Programming Details ==
The Querier polls the [[Programming_the_SPI|SPI module]] to poll the Temperature sensor chip and then the 8 channels of the ADC. The channels are shuffled by means of a simple counter (possibly starting from 111 then 000, 001 etc.) Each "Done" signal from the [[Programming_the_SPI|SPI module]] is passed back as a "Go" signal for the next poll. The [[FPGA_Registers#Temperature Register|appropriate registers]] are pulsed simultaneously to record the values for later transmission. As mentioned above, the ADC address returned by the SPI Module along with the voltage data is checked against the requested address. Mismatch results in the error value of 0xFFF recorded in lieu of the returned value.
=== Ports ===
* ''Clk'': [in] clock
* ''Rst: [in] asynchronous reset
[[Programming_the_SPI|SPI module]]'s return values
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Done'': [in] ; "Done" signal from the SPI Module
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle
* ''Temp_in'': [in ] SPI module's latched 10-bit temperature output bus
* ''ADC_in'': [in ] SPI module's latched 12-bit ADC output bus
* ''ADC_Ain'': [in ] SPI module's latched 3-bit ADC address output bus
Data request signals for the [[Programming_the_SPI|SPI module]]
* ''Go'': [out] "Go" signal
* ''T_iA'': [out] active-high Temp. sensor, active-low ADC selection line
* ''ADC_Aout'': [out] 3-bit ADC address line
Temperature and ADC value storage
* ''ADCregEn'': [out] write signal to ADC register
* ''ADCregA '': [out] 3-bit address selection for ADC register
* ''TempregEn'': [out] write signal to Temperature register
* ''Temp'': [out] Temperature value output to the Temperature register
* ''ADC'': [out] ADC value output to the ADC register
[[FPGA_Registers#State_Register|State Register]] Control Lines
* ''state_En'': [out] state register enable (write) signal
* ''state_D'': [out] (3-bit) state register input
* ''state_Q'': [in] (3-bit) state register output