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Line 92: − == (100) Poll Status == − − This block will have at least two functional blocks: one to poll the temperature sensor and one to poll the ADC. Its job is to update all status values from the status chips in preparation for transmission. Additionally, it converts all values to 16-bit two's-complement before storing locally. Once all status values have been updated it transitions to state 101. − − Currently we assume that data values will be stored in the FPGA. If data values will be stored on CP2200/1 Flash memory or other storage device, the interfaces and blocks will have to be adjusted appropriately. − − inputs − * ''Clk'': clock − * ''/Rst'': asynchronous, active-low reset − * ''State'': 3-bit state value − − internal signals − * ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'') − * ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle − − blocks − * '''ADC Poll''' − ** Updates values stored in the FPGA from the ADC. Obtains data from ADC, converts to 16-bit two's-complement, and stores. − ** inputs − *** ''Clk'': clock − *** ''/Rst'': asynchronous, active-low reset − *** ''Go'': go pulse to begin − ** outputs − *** - All ADC control lines - − *** ''A_Done'': goes high when reset/initialization process is complete, falls on ''Go'' pulse − *** ''En'': enable line for writing to the internal registers − *** ''Sel'': 3-bit select bus to specify which ADC channel data is available − *** ''Data'': 16-bit data bus to carry data to FPGA internal registers − * '''Temp Poll''' − ** Updates value stored in the FPGA from the temperature sensor. Obtains data from temperature sensor, converts to 16-bit two's-complement, and stores. − ** inputs − *** ''Clk'': clock − *** ''/Rst'': asynchronous, active-low reset − *** ''Go'': go pulse to begin − ** outputs − *** - All temperature sensor control lines - − *** ''En'': enable line for writing to the internal register − *** ''Data'': 16-bit data bus to carry data to FPGA internal registers − * '''Coordinator''' − ** Coordinates the completion of each polling cycle and notifies other blocks that the polling process is complete. − ** inputs − *** ''Clk'': clock − *** ''/Rst'': asynchronous, active-low reset − *** ''A_Done'': high when ADC is done polling − ** outputs − *** ''Done'': when ''A_Done'' goes high, ''Done'' pulses for one cycle; connects to state register as an enable − **: Note that the temperature sensor does not signal completion. That is because the temperature sensor need only update one value, while the ADC must update eight values. Thus it is known ahead of time that the temperature sensor will already be done by the time the ADC is done. − *** ''New_St'': new state to be written to the state register; goes to 101 while ''Done'' is high
Programming the Ethernet controller (view source)
Revision as of 19:01, 16 May 2008
, 19:01, 16 May 2008→Controller
[[FPGA_Reader|Packet Reader]] (Packet type inspection)
[[FPGA_Reader|Packet Reader]] (Packet type inspection)
[[FPGA_Transmitter|Packet Transmitter]]
[[FPGA_Querier|Querier (status query module)]]
== (101) Transmit "S" ==
== (101) Transmit "S" ==