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Line 68: − == Transceiver == − This block provides a level of abstraction between the precise CP2200/1 interface and a generalized interface seen by the internal blocks of the FPGA. This eliminates a need for the internal workings of the FPGA to be aware of the timing of the interface; hey simply order a start of transfer and wait for notification of the transfer's completion. The transceiver for its part initiates a read or write conversation with the CP2200/1 over the multiplex Intel bus upon request from the internals and returns data, if applicable, along with a "Done" pulse at the end of the conversation.+ − This unit serves as a bridge between the Ethernet Controller chip and the FPGA in terms of timing as well. The latter is run at the rate of its slowest client: the Temperature sensor which has a top recommended clock rate of 10 MHz. Given that CP2200/1 prefers 20 MHz, it was resolved that the FPGA will run on a 5 MHz clock subdivided from the Ethernet Controller's. The transceiver performs this subdivision and ensures data latching on the external and internal buses, as shown in the adjacent diagram. − − [[Image:MuxIntelTiming.png|frame|Multiplexed Intel Bus and internal I/O timing scheme enforced by FPGA clocks]] − − inputs − * ''fCLK'': "fast" (20MHz) clock − * ''/Rst'': asynchronous, active-low reset − * ''TxRx_Go'': pulse to begin a transmission − * ''TxRx_RiW'': read/write toggle: active-high read, active-low write − * ''TxRx_Ain'': 8-bit bus for address to read to/write from − * ''TxRx_Din'': 8-bit bus for data to write; ignored during a read − − outputs to internals − * ''Done'': pulse to signal completion of a transmission − * <s>''R/W_out'': read/write flag: active-high read, active-low write</s> − * <s>''A_out'': 8-bit bus for address of last read/write</s> − * ''D_out'': 8-bit bus for data of last read; internal systems should ignore for a write − * ''CLK'' : 5MHz clock for all internals subdivided from the master 20MHz clock. − − outputs to CP2200/1 − * ''/CS'': active-low chip select − * ''MotEn'': Motorola/Intel format toggle: active-high Motorola, active-low Intel − * ''MuxEn'': Multiplexed flag; not used for CP2201 − * ''ALE'': ALE strobe − * ''/Wr'': Active-low write flag − * ''/Rd'': Active-low read flag − − inouts − * ''AD'': 8-bit address and data bus − − For debugging purposes, a test input buffer will be added as stimulus for the combined FPGA simulation. This could take the form of a single packet or a full Ethernet Controller emulator. with the test waveform being injected either directly into the internal bus or on the Intel bus.
Programming the Ethernet controller (view source)
Revision as of 18:51, 16 May 2008
, 18:51, 16 May 2008no edit summary
With a controller this complex, the timing of signals must be inspected even more scrupulously than usual. In particular, simultaneous transitions of data and "Done" lines must be avoided. When possible, a one-cycle-delayed "Done" signal is used to ensure that the data lines have been stabilized. (All delays are implemented via the <tt>c_delay</tt> module which postpones the signal by one cycle via two sequential flip-flops, each shifting by half-cycle). When this is inconvenient (e.g. when writing to registers) the target component must not be enabled on rising edges on "Go" or the clock. The registers, for instance, have been designed to read values on the ''falling edge'' of the clock - middle of the "Go" pulse, safely after the data line transitions.
With a controller this complex, the timing of signals must be inspected even more scrupulously than usual. In particular, simultaneous transitions of data and "Done" lines must be avoided. When possible, a one-cycle-delayed "Done" signal is used to ensure that the data lines have been stabilized. (All delays are implemented via the <tt>c_delay</tt> module which postpones the signal by one cycle via two sequential flip-flops, each shifting by half-cycle). When this is inconvenient (e.g. when writing to registers) the target component must not be enabled on rising edges on "Go" or the clock. The registers, for instance, have been designed to read values on the ''falling edge'' of the clock - middle of the "Go" pulse, safely after the data line transitions.
[[FPGA_Transceiver Transceiver]]
== Registers ==
== Registers ==