Changes

=== Transceiver ===

=== Transceiver ===

This block provides a level of abstraction between the precise CP2200/1 interface and a generalized interface seen by the internal blocks of the FPGA. It takes information on the next transfer to carry out and returns information on the last transfer completed.  It has a pulse signal to begin a transfer and a pulse signal to notify of a completed transfer.  This eliminates a need for the internal workings of the FPGA to be aware of the timing of the interface; it simply begins a transfer and waits for notification of the transfer's completion. The transceiver is intended to function on the Multiplexed Intel bus format to communicate with the CP2200/1.

This block provides a level of abstraction between the precise CP2200/1 interface and a generalized interface seen by the internal blocks of the FPGA. This eliminates a need for the internal workings of the FPGA to be aware of the timing of the interface; hey simply order a start of transfer and wait for notification of the transfer's completion. The transceiver for its part initiates a read or write conversation with the CP2200/1 over the multiplex Intel bus upon request from the internals and returns data, if applicable, along with a "Done" pulse at the end of the conversation.

 

This unit serves as a bridge between the Ethernet Controller chip and the FPGA in terms of timing as well. The latter is run at the rate of its slowest client: the Temperature sensor which has a top recommended clock rate of 10 MHz. Given that CP2200/1 prefers 20 MHz, it was resolved that the FPGA will run on a 5 MHz clock subdivided from the Ethernet Controller's. The transceiver performs this subdivision and ensures data latching on the external and internal buses, as shown in the adjacent diagram.

 

[[Image:MuxIntelTiming.png|frame|Multiplexed Intel Bus and internal I/O timing scheme enforced by FPGA clocks]]

inputs

inputs

* ''CLK'': clock

* ''fCLK'': "fast" (20MHz) clock

* ''/Rst'': asynchronous, active-low reset

* ''/Rst'': asynchronous, active-low reset

* ''TxRx_Go'': pulse to begin a transmission

* ''TxRx_Go'': pulse to begin a transmission

* ''AD'': 8-bit address and data bus

* ''AD'': 8-bit address and data bus

=== Registers ===

=== Registers ===