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The modules involved in communication with with the Ethernet Controller chip as a means of bridging computer instructions with the on-board sensors serve as the core of the FPGA. The different tasks that need to be performed by these modules include
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* executing the complex board reset and address lookup sequence
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* polling for new packets and switching execution accordingly
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* collecting sensor information upon a status report request
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* programming the DAC upon a program packet receipt
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* building return packets
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In  our design, the modules involved with packet handling and interfacing with sensor chip controllers are organized by ''state''. A state register specifies the current stage of the process and only the corresponding module is allowed to act during that stage. Aside from defining a process sequence, the state serves as a complex "enable" signal for the modules, ensuring that only one module is driving the communication bus used to query the Ethernet Controller chip.
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= Interface =
 
= Interface =
  
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