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=== Non-State Components ===
 
=== Non-State Components ===
   −
==== transceiver ====
+
==== Transceiver ====
    
This block provides a level of abstraction between the precise CP2200/1 interface and a generalized interface seen by the internal blocks of the FPGA.  It takes information on the next transfer to carry out and returns information on the last transfer completed.  It has a pulse signal to begin a transfer and a pulse signal to notify of a completed transfer.  This eliminates a need for the internal workings of the FPGA to be aware of the timing of the interface; it simply begins a transfer and waits for notification of the transfer's completion.  The transceiver is intended to function on the Multiplexed Intel bus format to communicate with the CP2200/1.
 
This block provides a level of abstraction between the precise CP2200/1 interface and a generalized interface seen by the internal blocks of the FPGA.  It takes information on the next transfer to carry out and returns information on the last transfer completed.  It has a pulse signal to begin a transfer and a pulse signal to notify of a completed transfer.  This eliminates a need for the internal workings of the FPGA to be aware of the timing of the interface; it simply begins a transfer and waits for notification of the transfer's completion.  The transceiver is intended to function on the Multiplexed Intel bus format to communicate with the CP2200/1.
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* ''CLK'': clock
 
* ''CLK'': clock
 
* ''/Rst'': asynchronous, active-low reset
 
* ''/Rst'': asynchronous, active-low reset
* ''Go'': pulse to begin a transmission
+
* ''TxRx_Go'': pulse to begin a transmission
* ''R/W_in'': read/write toggle: active-high read, active-low write
+
* ''TxRx_RiW'': read/write toggle: active-high read, active-low write
* ''A_in'': 8-bit bus for address to read to/write from
+
* ''TxRx_Ain'': 8-bit bus for address to read to/write from
* ''D_in'': 8-bit bus for data to write; ignored during a read
+
* ''TxRx_Din'': 8-bit bus for data to write; ignored during a read
    
outputs to internals
 
outputs to internals
 
* ''Done'': pulse to signal completion of a transmission
 
* ''Done'': pulse to signal completion of a transmission
* ''R/W_out'': read/write flag: active-high read, active-low write
+
* <s>''R/W_out'': read/write flag: active-high read, active-low write</s>
* ''A_out'': 8-bit bus for address of last read/write
+
* <s>''A_out'': 8-bit bus for address of last read/write</s>
 
* ''D_out'': 8-bit bus for data of last read; internal systems should ignore for a write
 
* ''D_out'': 8-bit bus for data of last read; internal systems should ignore for a write
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==== temperature register ====
+
==== Temperature Register ====
 
A 16-bit register to store the most recent temperature data.
 
A 16-bit register to store the most recent temperature data.
 
inputs
 
inputs
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* ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
 
* ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
 
* ''En'': write enable
 
* ''En'': write enable
* ''D'': ten-bit data-in bus
+
* ''D'': 10-bit data-in bus
    
outputs
 
outputs
* ''Q'': ten-bit data-out bus
+
* ''Q'': 16-bit data-out bus to facilitate packaging into 2-byte words
      −
==== ADC registers ====
+
==== ADC Registers ====
 
A set of eight 16-bit registers to store the most recent ADC data.  Also includes a demultiplexer to select which register to write to.
 
A set of eight 16-bit registers to store the most recent ADC data.  Also includes a demultiplexer to select which register to write to.
 
inputs
 
inputs
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* ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
 
* ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
 
* ''En'': write enable
 
* ''En'': write enable
* ''S'': 3-bit select bus
+
* ''A'': 3-bit address
 
* ''D'': 12-bit data-in bus
 
* ''D'': 12-bit data-in bus
    
outputs
 
outputs
* ''Q'': 12-bit data-out bus; outputs data of register chosen by S bus
+
* ''Q'': 16-bit data-out bus; outputs data of register chosen by S bus
      −
==== DAC registers ====
+
==== DAC Registers ====
 
A set of 32/24/16 16-bit registers to store the most recent DAC data.  Also includes a demultiplexer to select which register to write to.
 
A set of 32/24/16 16-bit registers to store the most recent DAC data.  Also includes a demultiplexer to select which register to write to.
 
inputs
 
inputs
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* ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
 
* ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
 
* ''En'': write enable
 
* ''En'': write enable
* ''S'': 5/5/4-bit select bus
+
* ''A'': 5/5/4-bit address (currently set at 5-bit)
 
* ''D'': 14-bit data-in bus
 
* ''D'': 14-bit data-in bus
    
outputs
 
outputs
* ''Q'': 14-bit data-out bus; outputs data of register chosen by S bus
+
* ''Q'': 16-bit data-out bus; outputs data of register chosen by S bus
     
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