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mLine 1:
Line 1: − The VHDL files can be found [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-6-2007/ADC_VHDL.zip here]. − Line 39:
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== Interface ==
== Interface ==
** if 1, analog input range is 0 to V<sub>Reg</sub>
** if 1, analog input range is 0 to V<sub>Reg</sub>
* Coding: set to zero
* Coding: set to zero
** if 0, output is two's complement
** if 0, output is two's complement [http://en.wikipedia.org/wiki/Two%27s_complement]
** if 1, output is binary-coded decimal (BCD)
** if 1, output is binary-coded decimal (BCD)