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* ''D_in'': Serial data in line, for communications from the FPGA to the ADC.
* ''D_in'': Serial data in line, for communications from the FPGA to the ADC.
−On startup the ADC requires two "dummy" conversation that write all ones to the ADC and read garbage data from the ADC.
+On startup the ADC requires two "dummy" conversations that write all ones to the ADC and read garbage data from the ADC.
A typical conversation lasts for 16 clock cycles, sends 12 bits to the ADC, and receives 12 bits from the ADC. The 12-bit control register has the following format:
A typical conversation lasts for 16 clock cycles, sends 12 bits to the ADC, and receives 12 bits from the ADC. The 12-bit control register has the following format: