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| === (010) Idle === | | === (010) Idle === |
| + | |
| + | inputs: |
| + | * ''Clk'': clock |
| + | * ''/Rst'': asynchronous, active-low reset |
| + | * ''State'': 3-bit state value |
| + | * ''TxRx_A'': 8-bit address from transceiver |
| + | * ''TxRx_D'': 8-bit data from transceiver |
| + | * ''TxRx_Done'': pulse from transceiver to signal transfer complete |
| + | |
| + | internal signals |
| + | * ''S_En'': state enable, ''S_En'' <= not ''St(2)'' and ''St(1)'' and not ''St(0)'' |
| + | * ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle |
| + | |
| + | blocks |
| + | * '''Fetcher''' |
| + | ** Reads register 0x76 (INT0RD) by sending a read request to the transceiver |
| + | ** inputs |
| + | *** ''F_Go'': pulse to start request, ''F_Go'' <= ''Go'' or ''Loop'' |
| + | ** outputs |
| + | *** ''TxRx_Go'': ''Go'' line on transceiver |
| + | *** ''TxRx_R/W'': ''R/W'' line on transceiver, tied high (read) |
| + | *** ''TxRx_A'': ''A_in'' bus on transceiver, tied to 0x76 (0111 0110) |
| + | **** Note: ''D_in'' on transceiver is not used; assume this line defaults to zero |
| + | * '''Looper''' |
| + | ** Switch to determine if this state should loop on itself or continue to the next state. |
| + | ** inputs |
| + | *** ''S_En'': state enable |
| + | *** ''TxRx_Done'': ''Done'' pulse from transceiver |
| + | *** ''TxRx_Data'': ''D_out'' bus from transceiver |
| + | ** outputs |
| + | *** ''Loop'': pulse to repeat fetch cycle; ''Loop'' <= ''S_En'' and ''TxRx_Done'' and ''TxRx_Data(6)'' |
| + | *** ''Done'': pulse to finish state; connects to state counter as an enable in order to increment the state to 011; ''Done'' <= ''S_En'' and ''TxRx_Done'' and not ''TxRx_Data(6)'' |
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| === (011) Read Packet === | | === (011) Read Packet === |