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=== (010) Idle ===
 
=== (010) Idle ===
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inputs:
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* ''Clk'': clock
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* ''/Rst'': asynchronous, active-low reset
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* ''State'': 3-bit state value
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* ''TxRx_A'': 8-bit address from transceiver
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* ''TxRx_D'': 8-bit data from transceiver
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* ''TxRx_Done'': pulse from transceiver to signal transfer complete
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internal signals
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* ''S_En'': state enable, ''S_En'' <= not ''St(2)'' and ''St(1)'' and not ''St(0)''
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* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle
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blocks
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* '''Fetcher'''
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** Reads register 0x76 (INT0RD) by sending a read request to the transceiver
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** inputs
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*** ''F_Go'': pulse to start request, ''F_Go'' <= ''Go'' or ''Loop''
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** outputs
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*** ''TxRx_Go'': ''Go'' line on transceiver
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*** ''TxRx_R/W'': ''R/W'' line on transceiver, tied high (read)
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*** ''TxRx_A'': ''A_in'' bus on transceiver, tied to 0x76 (0111 0110)
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**** Note: ''D_in'' on transceiver is not used; assume this line defaults to zero
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* '''Looper'''
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** Switch to determine if this state should loop on itself or continue to the next state.
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** inputs
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*** ''S_En'': state enable
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*** ''TxRx_Done'': ''Done'' pulse from transceiver
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*** ''TxRx_Data'': ''D_out'' bus from transceiver
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** outputs
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*** ''Loop'': pulse to repeat fetch cycle; ''Loop'' <= ''S_En'' and ''TxRx_Done'' and ''TxRx_Data(6)''
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*** ''Done'': pulse to finish state; connects to state counter as an enable in order to increment the state to 011; ''Done'' <= ''S_En'' and ''TxRx_Done'' and not ''TxRx_Data(6)''
    
=== (011) Read Packet ===
 
=== (011) Read Packet ===
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