461
edits
Changes
Jump to navigation
Jump to search
Line 35:
Line 35: − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + + + − +
Programming the Ethernet controller (view source)
Revision as of 14:27, 19 July 2007
, 14:27, 19 July 2007no edit summary
inputs
inputs
* State: 3-bit state value
* ''State'': 3-bit state value
* D_En: DAC enable, assume held high/low by previous block
* ''D_En'': DAC enable, assume held high/low by previous block
* A_En: ADC enable, assume held high/low by previous block
* ''A_En'': ADC enable, assume held high/low by previous block
* E_En: Ethernet enable, assume held high/low by previous block
* ''E_En'': Ethernet enable, assume held high/low by previous block
internal signals
internal signals
* S_En: state enable, S_En <= not (St(2) or St(1) or St(0))
* ''S_En'': state enable, ''S_En'' <= not (''St''(2) or ''St''(1) or ''St''(0))
* Go: when S_En goes high Go pulses for one cycle
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle
* D_Go: DAC reset go pulse, D_Go <= Go and D_En
* ''D_Go'': DAC reset go pulse, ''D_Go'' <= ''Go'' and ''D_En''
* A_Go: ADC reset go pulse, A_Go <= Go and A_En
* ''A_Go'': ADC reset go pulse, ''A_Go'' <= ''Go'' and ''A_En''
* E_Go: Ethernet reset go pulse, E_Go <= Go and E_En
* ''E_Go'': Ethernet reset go pulse, ''E_Go'' <= ''Go'' and ''E_En''
blocks
blocks
* DAC Reset:
* '''DAC Reset'''
** Resets and initializes the DAC.
** Resets and initializes the DAC.
** inputs
** inputs
*** Clk: clock
*** ''Clk'': clock
*** /Rst: asynchronous, active-low reset
*** ''/Rst'': asynchronous, active-low reset
*** D_Go: go pulse to begin reset/initialization process
*** ''D_Go'': go pulse to begin reset/initialization process
** outputs
** outputs
*** - All DAC reset/initialization control lines -
*** - All DAC reset/initialization control lines -
*** D_Done: goes high when reset/initialization process is complete, falls on D_Go pulse
*** ''D_Done'': goes high when reset/initialization process is complete, falls on ''D_Go'' pulse
* ADC Reset:
* '''ADC Reset'''
** Resets and initializes the ADC.
** Resets and initializes the ADC.
** inputs
** inputs
*** Clk: clock
*** ''Clk'': clock
*** /Rst: asynchronous, active-low reset
*** ''/Rst'': asynchronous, active-low reset
*** A_Go: go pulse to begin reset/initialization process
*** ''A_Go'': go pulse to begin reset/initialization process
** outputs
** outputs
*** - All ADC reset/initialization control lines -
*** - All ADC reset/initialization control lines -
*** A_Done: goes high when reset/initialization process is complete, falls on A_Go pulse
*** ''A_Done'': goes high when reset/initialization process is complete, falls on ''A_Go'' pulse
* Ethernet Reset:
* '''Ethernet Reset'''
** Resets and initializes the Ethernet controller.
** Resets and initializes the Ethernet controller.
** inputs
** inputs
*** Clk: clock
*** ''Clk'': clock
*** /Rst: asynchronous, active-low reset
*** ''/Rst'': asynchronous, active-low reset
*** E_Go: go pulse to begin reset/initialization process
*** ''E_Go'': go pulse to begin reset/initialization process
** outputs
** outputs
*** - All Ethernet reset/initialization control lines -
*** - All Ethernet reset/initialization control lines -
*** E_Done: goes high when reset/initialization process is complete, falls on E_Go pulse
*** ''E_Done'': goes high when reset/initialization process is complete, falls on ''E_Go'' pulse
* Coordinator
* '''Coordinator'''
** Coordinates the completion of each reset cycle and notifies other blocks that the reset process is complete. Has internal signal: Flag <= (D_Done or not D_En) and (A_Done or not A_En) and (E_Done or not E_En)
** Coordinates the completion of each reset cycle and notifies other blocks that the reset process is complete.
** inputs
** inputs
*** Clk: clock
*** ''Clk'': clock
*** /Rst: asynchronous, active-low reset
*** ''/Rst'': asynchronous, active-low reset
*** D_En: high when DAC is to be reset
*** ''D_En'': high when DAC is to be reset
*** D_Done: high when DAC is done resetting
*** ''D_Done'': high when DAC is done resetting
*** A_En: high when ADC is to be reset
*** ''A_En'': high when ADC is to be reset
*** A_Done: high when ADC is done resetting
*** ''A_Done'': high when ADC is done resetting
*** E_En: high when Ethernet controller is to be reset
*** ''E_En'': high when Ethernet controller is to be reset
*** E_Done: high when Ethernet controller is done resetting
*** ''E_Done'': high when Ethernet controller is done resetting
** internal signals
*** ''Flag'' <= (''D_Done'' or not ''D_En'') and (''A_Done'' or not ''A_En'') and (''E_Done'' or not ''E_En'')
** outputs
** outputs
*** Done: when Flag goes high, Done pulses for one cycle; connects to state counter as an enable (thereby incrementing the state to 001)
*** ''Done'': when ''Flag'' goes high, ''Done'' pulses for one cycle; connects to state counter as an enable (thereby incrementing the ''State'' to 001)