Changes

* Full reset: This resets all chips on the board (except for the FPGA; that should reset only during a power-up) together.  This will contain no data.

* Full reset: This resets all chips on the board (except for the FPGA; that should reset only during a power-up) together.  This will contain no data.

* Selective reset: This will have flags to reset the Ethernet chip, the ADC, the temperature sensor, and the DAC.  Combinations of flags allow a selective reset of any combination of the four chips.  This will contain four flags which can be packaged into a single byte.

* Selective reset: This will have flags to reset the Ethernet chip, the ADC, the temperature sensor, and the DAC.  Combinations of flags allow a selective reset of any combination of the four chips.  This will contain four flags which can be packaged into a single byte.

The first data byte will be an ASCII '''R''': 0x52, 0101 0010.  For a full-reset-only design, all remaining bytes in the packet will be padding that the FPGA can ignore.  For a selective-reset design, the second data byte will contain the four flags, and all bytes after that will be padding.

The first data byte will be an ASCII '''R''': 0x52, 0101 0010.  For a full-reset-only design, all remaining bytes in the packet will be padding that the FPGA can ignore.  For a selective-reset design, the second data byte will contain the four flags, and all bytes after that will be padding.  A selective-reset design allows a form of, "Are you awake," query to the board: Send a reset packet with all reset flags turned off; the system will not reset any devices but will still respond with an "I" packet.

==== "I" packet: initialization complete ====

==== "I" packet: initialization complete ====