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Programming of the FPGA is an ongoing project, so more questions may be added as the project develops.
Programming of the FPGA is an ongoing project, so more questions may be added as the project develops.
* What is the clock speed of the FPGA? Timing constraints must be taken into account to link the multiple blocks.
* What is the clock speed of the FPGA? Timing constraints must be taken into account to link the multiple blocks.
* Current designs (11 July, 2007) account for normal activity. Need to design modules/logic for startup and initialization of each component. This should not be only on startup; we should be able to send a reset packet over Ethernet to trigger a reinitialization of each chip.
* Current designs (11 July, 2007) account for normal activity. Need to design modules/logic for startup and initialization of each component. This should not be only on startup; we should be able to send a reset packet over Ethernet to trigger a reinitialization of each chip. ''Work in progress'': see [[Reset and Initialization]].
* Do the parts work on falling or rising edges of the clock? Most VHDL designs are currently on rising edges, but this can be easily corrected.
* Do the parts work on falling or rising edges of the clock? Most VHDL designs are currently on rising edges, but this can be easily corrected.
* The temperature sensor and the ADC share the same SPI-like bus lines; can they be combined into a single VHDL design?
* The temperature sensor and the ADC share the same SPI-like bus lines; can they be combined into a single VHDL design?
* A core VHDL module is needed to tie all the components together. The Ethernet controller module may take on the role of FPGA core.
== Component code ==
== Component code ==