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Following this are 64 (or 48 or 32) bytes of programming data. The first two bytes are for channel 31 (or 23 or 15) and the last two bytes are for channel 0. Each channel has 14 bits, so the format is two leading zeros and 6 MSB of data is the first byte, then 8 LSB of data in the second byte. All channels are present in the packet, but only those marked in the mask will be programmed; all other bytes will be ignored and can take on any value. The total size of a programming packet is:
Following this are 64 (or 48 or 32) bytes of programming data. The first two bytes are for channel 31 (or 23 or 15) and the last two bytes are for channel 0. Each channel has 14 bits, so the format is two leading zeros and 6 MSB of data is the first byte, then 8 LSB of data in the second byte. All channels are present in the packet, but only those marked in the mask will be programmed; all other bytes will be ignored and can take on any value. The total size of a programming packet is:
{| align="center" cellpadding="4" border="0" cellspacing="0" style="text-align:center"
{| align="center" cellpadding="8" border="0" cellspacing="4" style="text-align:center"
! Number of channels
! Number of channels
! Bytes per Packet
! Bytes per Packet
|}
|}
Since the minimum number of data bytes in a packet is 46, the packet may need to be padded if only 16 channels are to be used. Padding may not be necessary if the PC includes layer 3 and layer 4 data.
Since the minimum number of data bytes in a packet is 46, the packet may need to be padded if only 16 channels are to be used. Padding may not be necessary if the PC includes layer 3 and layer 4 data.
==== "D" packet: DAC setup complete ====
This is the packet sent from the FPGA to the PC to confirm that the DAC has been programmed to specifications. The first byte of this packet is an ASCII '''D''': 0x44, 0100 0100. The next 64 (or 48 or 32) bytes are the values of each DAC channel. As before, the format is two leading zeros and 6 MSB of data in the first byte and 8 LSB of data in the second byte, channel 31 (or 23 or 15) first, channel 0 last. This confirms to the PC that the data was programmed according to specification and helps synchronize the control board and the PC. All channels are reported back, not just those that were reprogrammed during this conversation. This will require that the FPGA (or the RAM in the Ethernet chip) store the values of the DAC channels, as the DAC has no interface to report back the value of a given channel. The size of this packet will be 4 (or 3 or 2) bytes less than for the corresponding programming packet.