Changes

You also see a shorthand that has been pre-defined for you: rising_edge.  There is also falling_edge.  These combine the ''event'' command with a specification of which direction the event happened (transition up or transition down).  Sequential logic makes extensive use of rising_edge and falling_edge.  Also note the else clause.  What is the point of having ''delayed'' loop back on itself?  This is to help the synthesizer along.  VHDL has some quirks and doesn't appreciate an if without an else.  So even if nothing happens, you always want to put that else clause in there and have all the signals in question loop back on themselves.  Otherwise the synthesizer goes crazy and adds latches left and right which at best make your design hideously large and unwieldy and at worst make your design completely nonfunctional.

You also see a shorthand that has been pre-defined for you: rising_edge.  There is also falling_edge.  These combine the ''event'' command with a specification of which direction the event happened (transition up or transition down).  Sequential logic makes extensive use of rising_edge and falling_edge.  Also note the else clause.  What is the point of having ''delayed'' loop back on itself?  This is to help the synthesizer along.  VHDL has some quirks and doesn't appreciate an if without an else.  So even if nothing happens, you always want to put that else clause in there and have all the signals in question loop back on themselves.  Otherwise the synthesizer goes crazy and adds latches left and right which at best make your design hideously large and unwieldy and at worst make your design completely nonfunctional.

Now let's take a look at the second process.

Now let's take a look at the second process.