Changes

The FPGA is the hub of the digital control board.  All components communicate through the FPGA and are controlled by the FPGA.  The chip we plan to use is the [http://www.xilinx.com/products/silicon_solutions/fpgas/spartan_series/spartan3a_fpgas/index.htm Xilinx Spartan-3A] FPGA.  The Spartan line of FPGAs are low-cost chips well-suited for small designs such as this.  The 3A model is optimized for I/O and includes a large number of I/O pins, which will be beneficial considering the amount of interconnect relative to the amount of logic.  A currently open question is which size of FPGA to choose.  The total number of system gates is 50k, 200k, 400k, 700k, or 1400k.  The likely method of choosing the proper FPGA is to design the [http://en.wikipedia.org/wiki/Hardware_description_language HDL] and synthesize it, then decide on a model based on number of logic cells and I/O pins required by the synthesized HDL.

The FPGA is the hub of the digital control board.  All components communicate through the FPGA and are controlled by the FPGA.  The chip we plan to use is the [http://www.xilinx.com/products/silicon_solutions/fpgas/spartan_series/spartan3a_fpgas/index.htm Xilinx Spartan-3A] FPGA.  The Spartan line of FPGAs are low-cost chips well-suited for small designs such as this.  The 3A model is optimized for I/O and includes a large number of I/O pins, which will be beneficial considering the amount of interconnect relative to the amount of logic.  A currently open question is which size of FPGA to choose.  The total number of system gates is 50k, 200k, 400k, 700k, or 1400k.  The likely method of choosing the proper FPGA is to design the [http://en.wikipedia.org/wiki/Hardware_description_language HDL] and synthesize it, then decide on a model based on number of logic cells and I/O pins required by the synthesized HDL.

=== The Ethernet controller ===

=== The Ethernet controller ===

After researching a variety of communication buses, including USB, I²C, FireWire, and various others, it was decided that the best choice would be [http://en.wikipedia.org/wiki/Ethernet Ethernet].  Ethernet is based on a multi-layer protocol, which each higher layer adding more advanced capabilities.  Only layers one and two are necessary for our purposes, being a local network not connected to a true internet.  We have selected the Silicon Laboratories' CP2200/1 Ethernet controller.  The CP2200 and CP2201 are the same chip with the differences lying (primarily) in packaging and I/O pin count.  Likely the CP2201 (the smaller chip) will prove sufficient, as of June, 2007 that decision has not been finalized.  The CP2200/1 supplied layers one and two automatically and can interface with the FPGA through a parallel bus described by the CP2200/1 data sheet.

After researching a variety of communication buses, including USB, I²C, FireWire, and various others, it was decided that the best choice would be [http://en.wikipedia.org/wiki/Ethernet Ethernet].  Ethernet is based on a multi-layer protocol, which each higher layer adding more advanced capabilities.  Only layers one and two are necessary for our purposes, being a local network not connected to a true internet.  We have selected the Silicon Laboratories' CP2200/1 Ethernet controller.  The CP2200 and CP2201 are the same chip with the differences lying (primarily) in packaging and I/O pin count.  Likely the CP2201 (the smaller chip) will prove sufficient, as of June, 2007 that decision has not been finalized.  The CP2200/1 supplied layers one and two automatically and can interface with the FPGA through a parallel bus described by the CP2200/1 data sheet.

=== The DAC ===

=== The DAC ===

The purpose of the control board is to allow remotely programmable bias voltages for the SiPMs.  For this purpose a DAC is required.  The current design of the tagger microscope calls for 16 SiPMs per electronics card.  Various designs were considered, but based on availability of components in the 50V range (DACs and op-amps primarily) the most suitable choice found was the Analog Devices' AD5535.  It can go up to 200V with a resolution of 14 bit (roughly 12mV at 200V scale, roughly 3mV at a 50V scale) on 32 channels.  As there are so many channels built in to this system, the tagger may be slightly restructured so as to include 32 SiPMs per board instead of 16 per board.  This DAC defines its own serial interface for communication with the FPGA.

The purpose of the control board is to allow remotely programmable bias voltages for the SiPMs.  For this purpose a DAC is required.  The current design of the tagger microscope calls for 16 SiPMs per electronics card.  Various designs were considered, but based on availability of components in the 50V range (DACs and op-amps primarily) the most suitable choice found was the Analog Devices' AD5535.  It can go up to 200V with a resolution of 14 bit (roughly 12mV at 200V scale, roughly 3mV at a 50V scale) on 32 channels.  As there are so many channels built in to this system, the tagger may be slightly restructured so as to include 32 SiPMs per board instead of 16 per board.  This DAC defines its own serial interface for communication with the FPGA.

=== The ADC ===

=== The ADC ===

In order to monitor the voltage levels of the power lines, an ADC is to be included in the design.  The Analog Devices' AD7928 is an eight-channel ADC.  Based on the selection of components there are six necessary power lines and two necessary grounds, so the AD7928 is capable of monitoring the entire system if need be.  It uses a serial protocol that is compatible with the SPI bus to communicate with the FPGA.

In order to monitor the voltage levels of the power lines, an ADC is to be included in the design.  The Analog Devices' AD7928 is an eight-channel ADC.  Based on the selection of components there are six necessary power lines and two necessary grounds, so the AD7928 is capable of monitoring the entire system if need be.  It uses a serial protocol that is compatible with the SPI bus to communicate with the FPGA.

=== Temperature sensor ===

=== Temperature sensor ===

In order to monitor the ambient temperature, a temperature sensor is to be included in the design.  The Analog Devices' AD7314 has ten-bit resolution on temperature and is compatible with the SPI bus for communication with the FPGA.

In order to monitor the ambient temperature, a temperature sensor is to be included in the design.  The Analog Devices' AD7314 has ten-bit resolution on temperature and is compatible with the SPI bus for communication with the FPGA.