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You can see that ISE has established a hierarchy of files. The DAC_box has a DAC_controller and a DAC_emulator. The DAC_controller has a DAC_hold19, a DAC_shiftreg, and a DAC_delay, and the DAC_emulator part list is collapsed. In front of each of these files lower in the hierarchy there is a u number. The u number is a shorthand designation of which part is which (discussed in [[VHDL:_The_real_code#Putting_it_together:_components|VHDL:_The_real_code]]). Your files can appear in multiple places, as well. For example, the DAC_subemulator (no u number because it is an independent part not used in the DAC_box) has a DAC_hold19 and a DAC_shifter.
You can see that ISE has established a hierarchy of files. The DAC_box has a DAC_controller and a DAC_emulator. The DAC_controller has a DAC_hold19, a DAC_shiftreg, and a DAC_delay, and the DAC_emulator part list is collapsed. In front of each of these files lower in the hierarchy there is a u number. The u number is a shorthand designation of which part is which (discussed in [[VHDL:_The_real_code#Putting_it_together:_components|VHDL:_The_real_code]]). Your files can appear in multiple places, as well. For example, the DAC_subemulator (no u number because it is an independent part not used in the DAC_box) has a DAC_hold19 and a DAC_shifter.
== Synthesis ==
[[Image:Sources Synthesis-Implementation.PNG|thumb|left|125px|The Sources box in the Synthesis and Implementation view.]]
Those of you familiar with computer programming may think of this step as "compiling", but since you're not generating an executable file it's not really the same thing. Synthesis is the step that takes your VHDL code and generates from it a schematic for your circuit.
Once you've written your code and are ready to see how the schematic looks, go up to the Sources box and set it as the top module. Then go down to the '''Processes''' box and double click on "Synthesize - XST".